Jeff Loyer

Signal and Power Integrity Product Manager at Altium Jeff Loyer is the Signal and Power Integrity Product Manager at Altium. Prior to joining Altium, he spent more than 20 years as an engineer at Intel, the last 10 as signal integrity lead for their server divisions. While at Intel, he led work groups which significantly impacted the industry’s high-speed PCB design practices, including work on the Fiberweave Effect, copper roughness, environmental effects on insertion loss, and insertion loss control and measurement (inventor of SET2DIL).

  • Is IPC-2152 Holding Your Power Integrity Back?

    Is IPC-2152 Holding Your Power Integrity Back?

    For most designers, the Power Distribution Network (PDN) is a foreign and intimidating part of the PCB design process. But achieving optimal PDN performance is not as complicated as it seems. For...

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  • DC Analysis of a PDN: Essential for the Digital Designer

    DC Analysis of a PDN: Essential for the Digital Designer

    As PCBs become increasingly miniaturized, engineers are commonly faced with incorporating multiple power planes on the same layer. While this design practice introduces coupling issues, the real...

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