The mere mention of the “Orient Express” conjures up images shrouded in mystery and intrigue. Spies often conducted their business during the 80-hour trip from Paris to Constantinople. Kings rode living and sleeping cars rivaled Europe’s finest hotels with wooden paneling, silk sheets, and deluxe leather armchairs.
PCI Express does not have the same aura as the “Orient Express” but does allow the high bandwidth communication between devices, motherboards, and other hardware. The only spies or kings that ride on the PCI Express exist within video games supported by PCIe powered video cards.
Getting Acquainted with the Express
Although no standard locomotive existed for the Orient Express, locomotives—such as the CSD 555.0—that had large diameter drive wheels pulled the train.
Peripheral Component Interconnect Express (PCIe or PCI-E) serves as the standard internal interface for computer motherboards and operates as a serial interface on a dual simplex bus. The PCI Express topology includes a transmitter located on one device and a receiver located on a second device. High-speed data transfer through AC-coupled, low-voltage differential signal (LDVS) lines and point-to-point connections. The use of external discrete capacitors for AC coupling isolates the DC voltage component from the transmitter to the receiver.
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PCI-E electromechanical specifications designate transmit (TX) originating signals as “PET” and receive (RX) signals as “PER”. Because PCIe uses a dual-simplex interface, connections consist of one differential pair dedicated to transmitted D+ and D- signals and a separate pair dedicated to received D+ and D- signals. PCIe operates through upstream devices—such as host memory controller hub chipset—and downstream devices. Examples of downstream devices include add-in cards or components.
Each set of transmit and receive differential pairs makes up a lane. Lanes exist within the links seen between upstream and downstream devices. In turn, each lane includes an upstream channel and a downstream channel. Each channel consists of one differential pair of signals.
Transmitters and receivers grouped as a signal interface make up a port. Every upstream device includes a downstream port while every downstream device includes an upstream port. Each port and its lanes form a link.
PCI-E links form through the connection of an upstream device TX and RX differential pairs to the RX and TX differential pairs of a downstream device. With PCIe, a device connected to the end of a link hierarchically closer to the root of the RX and TX differential pairs serves as an upstream device. Downstream devices connect at the end of the PCIe link hierarchically further from the PCIe root.
Routing the Express
Routing for PCIe follows the same general guidelines for preventing crosstalk and maintaining impedance targets applied to differential pair signaling. In addition to focusing on differential pair width and spacing, your design should include a solid reference plane ground. Because of the amount of coupling seen with PCI-e circuits, splits, voids, and other discontinuities in the reference plane can introduce problems with AC common mode voltage, signal quality, and EMI.
PCI-e circuits also require special attention for routing near the edge of the reference plane. You should provide a 20-mil or greater air gap to the edge of the reference plane when the traces run parallel to the plane edge. PCI-e traces on an add-in card must reference to the ground plane.
Being able to choose how to map your pins together will benefit your designs immensely.
To reduce the problems with loss and jitter, keep your trace widths at 5 mils and keep trace lengths (from pin-to-pin) as short as possible. Using wide traces lessens the susceptibility to skin effect loss while keeping material costs low. A proportional relationship between decreased trace width and increased skin effect loss exists. Trace routing lengths from chip to chip cannot exceed 15.5 inches while trace lengths from a chipset to a connector cannot exceed 12 inches.
Because of the opportunity for signal reflections, you should stay away from using stubs in your PCB designs. Minimize the number of vias to no more than six and use smaller via geometries to lower parasitic losses. Differential pair signaling also requires precise spacing to minimize crosstalk. When using microstrip, the intra-pair air gap spacing should measure at 7 mils. Stripline requires 5 mils of air gap spacing. The pair-to-pair spacing must remain at less than 20 mils.
In addition to spacing, PCI-e also requires symmetrical PCB trace routing. Maintain the symmetry of the routing by placing AC capacitors side-by-side and by having side-by-side breakout from package pins. Use serpentine routing to compensate for length mis-matches and for any non-symmetrical breakout patterns. You should avoid tight bends in the trace and match the number of left and right bends when designing you PCI-e board.
Was the Spy Wearing a Bowtie?
Although we don’t know if spies riding the Orient Express wore bowties, the PCI-E topology can feature bowties when a link physically routes on a PCB. Bowtie topologies can occur when the D+ and D- signals from a transmitter must crisscross to connect to the D+ and D- signals of a receiver or when the differential pairs must cross to correctly connect from device to device. Bowties can also result when lanes cross.
PCIe designs compensate for bowtie scenarios through polarity inversion and optional lane reversals. If the receiver detects a polarity inversion, it inverts the received data on the differential pair. As a result, the lane functions when a transmitter D+ signal connects to the receiver D- signal. If supported by the devices, lane reversal reorders the lanes that connect between transmitting and receiving devices.
If you’re looking for strong PCB design software which can offer the routing you need to get through any layout, consider Altium’s CircuitStudio. It has the tools you need to make your designs a breeze.
If you’re interested in learning more, talk to an expert at Altium today.
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