Layout Guidelines for Embedded Power Supplies

December 27, 2018 Altium Designer

Computer power supply

I don’t get out to raucous parties as much as did in my 20’s. The thought of yelling over other people just to have a conversation is about as enticing as getting a tooth pulled.

Crosstalk doesn’t just kill the mood at a party, it can ruin the functionality of electronic systems. Most PCB designers worry more about crosstalk between signals traces, but your power supply and power components can have an even greater impact. Thankfully, some simple design choices and layout guidelines can keep your power output and signals clean in your PCB.

 

Signal Integrity and Power Integrity

These two terms are sometimes used interchangeably by designers and engineers, and the novice PCB designer may see these two aspects of PCB design as unconnected issues. Unfortunately, PCBs are not so simple that power integrity and signal integrity can be considered in isolation.

In reality, some important signal problems actually originate from power integrity problems. Power integrity tolerances have become tighter over time as transistor density in digital systems increases (thank you very much, Gordon Moore). Individual transistors have scaled down in size, and older power supplies with large output fluctuations or ripple voltage can wreak havoc on digital signals due to involuntary switching.

Power rails on modern PCBs with sensitive components should only be fed with a power source that has from 1% to 5% total variation in the output power. For low current circuits or any board where signal integrity is a major concern, it is a good idea to try and reduce power output variations to an even lower level, if possible. Your signal traces and your power supply/power rails can have crosstalk, which exacerbates power integrity problems.

But you might be wondering, how does a DC power source induce crosstalk in an AC signal trace? The AC components in the power supply output can induce a current in a nearby trace. During the PCB design phase, a good simulation tool can help you diagnose crosstalk issues in traces and power rails before you send your board off for production. If an AC signal trace is the aggressor trace, it can contribute to power fluctuations thanks to parasitic inductance and capacitance.

 Blue stethoscope on a tablet

Blue stethoscope on a tablet

 

Your Power Supply as an Aggressor in Crosstalk

If you’ve ever connected the output from your power supply to an oscilloscope, you’ll find that there are several AC components present in the power supply output. If you’re using an AC adapter, the full wave rectifier outputs a DC signal with some fluctuation. The capacitor in the rectifier charges and discharges twice during a single oscillation. If you look at the signal in the frequency domain, you’ll see a band near 120 Hz (100 Hz if you’re in Europe) if your adapter is plugged into a wall outlet.

Switching power supplies also produce power with a ripple voltage. If you look at the power spectrum for the output power signal, you’ll see another frequency component due to the switching action in the power supply. Both of these components are apparent on an oscilloscope. You can also simulate the magnitude of these components in your PCB using a good signal simulator package.

These components can induce crosstalk in signal traces, and vice versa. While you could always use metal can shielding on sensitive components and even groups of traces, using the right layout strategy can prevent the need to sensitive shielding in the presence of noisy power components.

 

A PCB Layout Plan for Reducing Noise

When your DC power supply is embedded with your board, the power supply output should be located close to the devices receiving the load as this will help minimize IR loss and interconnect impedance. If you’re embedded power supply will generate a lot of heat, you should try to place any cooling fans near the power supply. A word of caution with cooling fans: these components can also create noise in nearby signal traces, so sensitive traces need to be shielded against this new source of noise.

If you’re planning a multi-layer board, the DC ground or input/output power planes should be located between the top component layer that contains and the inner layer that contains traces carrying sensitive signals. The DC ground and/or power planes act as a shield that blocks the inner signal traces from noise in the power rails and any power components on the top layer.

Waveform measurement with an oscilloscope

Waveform measurement with an oscilloscope

Separating these groups of traces into different layers lets you focus on reducing noise on the power layer without having to worry about this noise being induced in sensitive traces in the inner signal layer. Judicious use of capacitors between the DC power source and its ground reference plane helps regulate the output power.

In the inner signal layers, the right routing strategy on your PCB can be used to reduce crosstalk between signal traces. Routing traces as differential pairs can reduce crosstalk between pairs, but routing all your differential pairs along the same direction is best for suppressing near-end crosstalk (NEXT). If far-end crosstalk (FEXT) is significant between multiple differential pairs, a better option is to use interleaved routing. In interleaved routing, successive differential pairs is routed in the reverse direction.

With all the power and signal integrity problems that can arise in modern PCBs, your PCB design software should include all the analysis tools you need to diagnose problems before you move to production. A great PCB design package like Altium Designer® has all of these tools and more. The PDN Analyzer™  and other signal analysis tools help ensure your device will function as designed.

You can download a free trial if you’re interested in learning more about Altium ’s layout, simulation, and analysis features. Talk to an Altium expert today to learn more.

About the Author

Altium Designer

PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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