Development of the world’s first DDR5 RAM was announced just 1 year ago, with peak speed of 5200 MT/sec/pin (compare that to 3200 MT/sec/pin with DDR4) at 1.1 V. Full-scale production is set to begin in 2020, and demand for this new generation of memories with 8, 16, and 32 GB capacities will quickly outpace that for earlier generations. JEDEC rates DDR5 speeds up to 6400 MT/sec/pin, with bandwidth increased up to 300 GB/s.
The faster speeds, lower supply voltages, and higher channel losses place even stricter margins and tolerances in DDR5 PCB design. This places tighter constraints on standard design practices like impedance control, regulation of channel losses, and power integrity. The new overhauled architecture will help solve signal degradation somewhat, although designers will still need to be aware of best practices for routing and layout. There is a lot to cover in this area, but for now we’ll focus on the essential layout and routing aspects that will help ensure signal integrity in DDR5.
Say Hello to Equalization
One of the biggest changes (in my opinion) to DDR architecture is the use of equalization to overcome channel losses and dispersion in DDR5 boards. Attenuation dispersion in PCB materials causes a trace to act like a low pass filter as higher frequencies experience greater losses than lower frequencies. Attenuation dispersion, combined with refractive index dispersion, distorts signals in such a way that the rise and fall time appear to be slowed down and the pulse shape appears to be rounded off.
DDR5 will continue to use single-ended nets, but with much shorter channel length than a typical SerDes channel. The shorter channel length in DDR5 buses means that channels are dominated by reflection rather than insertion loss. At the high speeds present in DDR5 channels, reflection-dominant behavior and dispersion combine to produce significant intersymbol interference (ISI) if traces are not properly terminated. ISI causes signal levels to appear distorted in addition to the shape distortion due to dispersion and reflections, and each digital pulse starts to look like a Gaussian pulse at the receive side in an unequalized channel. The end result is that the eye diagram for the channel starts to close as losses and dispersion-related distortion accumulate.
Conceptually, the easiest way to overcome distortion in digital signals is to pass the attenuated signal through a high pass filter. This is why a parallel RC filter can be used as a simple equalizer. In order to overcome signal distortion and ISI, an equalization scheme is incorporated into the DRAM architecture, either at the transmit or receive side, similar to the case of some DDR3 and DDR4 controllers. Decision feedback equalization (DFE) or continuous time linear equalization (CTLE) can be used at the receive side, or feed-forward equalization (FFE) can be used at the transmit side. Note that CTLE is not ideal for reflection-dominated channels, thus some designs will use DFE and/or FFE for equalization.
A DDR PCB layout should be designed with the number taps in the equalizer considered. In general, using an equalizer with a larger number of taps will help ensure a larger height eye diagram (~500 mV is typical), but this does not necessarily increase the eye width. Traces should be carefully sized as a function of the number of taps in the equalizer on a DRAM chip. A low-loss high speed laminate can be beneficial for bringing BER below 10-12.
Eye diagram measurement.
Other Signal Degradation Sources
There are other sources of noise in DDR5 channels that become even more problematic than in previous generations, especially given the higher speeds required to accommodate the higher data/clock rates (e.g., 3.2 GHz.in DDR5-6400). Despite the use of equalization to overcome channel losses and distortion, extremely precise termination and impedance control is required to ensure equalization can provide signal recovery. In such low voltage devices, these impedance mismatch constraints become ever more critical to ensuring a low BER.
On the simulation side, a post-layout crosstalk simulation tool that draws on IBIS models for your components can help you evaluate signal integrity in your DDR5 signal channels. Analyzing reflections is also critical, especially in such a high-speed, reflection-dominated multi-drop topology found in DDR5. If you’re like me, and you enjoy this type of analysis by hand, you can determine channel behavior from an impulse response function (IRF) measurement or simulation results. You can easily determine BER and signal behavior in the presence of various noise sources through simple convolution between an arbitrary bitstream and the IRF.
Power delivery is also critical in DDR5 PCB design. DDR5 chips will include a power management IC that receives 12 V and outputs 1.1 V to the DIMM ICs. This shifts power integrity concerns to the DDR5 module level and away from the motherboard. Considering the higher clock and data rates (as well as associated faster rise time), the PDN must have a flat impedance spectrum out to higher frequencies in order to ensure power integrity.
GDDR5 for a GPU
The powerful PCB layout and routing tools in Altium Designer® are designed for applications like SerDes channels, DDR5 PCB design, and other advanced areas. Altium Designer includes a powerful stackup manager with a field solver for controlling impedance in your board during routing, and you’ll have access to post-layout simulation tools that will help you spot signal integrity problems in your board.
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About the AuthorMore Content by Zachariah Peterson