Layer stack up is one of the most fundamental parts of component design. The order of arrangement and stack up is very important in ensuring that the design comes out as expected for a number of technical and electronic reasons. Among these reasons are the EMC, reduction of impedance incompatibility and other factors. That being said, we will discuss a few features that should be taken into consideration when a layer stack up is being developed for high-speed design.
Fig. 1 : An example of a 6-layer stack up composed of pre-preg material (black),
core material (blue) and copper layers (orange).
Let us focus on a typical 6-layer stack up, as shown above (Fig. 1), which is appropriate for high speed design. In total, are 2 planes and 4 routing layers; the black lines, blue lines and orange lines all represent the pre-preg (pre-impregnated) material, core material and copper layers, respectively.
To begin, you need to ensure that your high-speed signals and plane layers are tightly coupled together. To achieve this, the core materials must be as thin as possible. The need for core materials here is essentially due to the nature of this being an impedance-driven arrangement. As such, a very flat surface must be used to guarantee constant impedance across the length of the routed wires.
Next, the outside layers need to be pre-pregged to the entire stack up. These layers are suitable for low-speed signals such as analog signal processing and any other application that doesn’t require much impedance drive. The pre-pregged materials are to be used at the center of the stack up to build the stack up to the appropriate final thickness of for the board, which will generally be around 62 mils. When developing the layer stack up, you will need to work with the fabricator. In order to be able to effectively communicate with them, you will need to be aware of the fabricator’s frequently stocked materials. This is essential to ensuring that the overall cost of the board is decent, as a demand for unavailable materials may force the fabricator to place a special order that would subsequently raise the cost of the board.
Fig. 2 : Upper portion of the stack up
Fig. 3 : Lower portion of the stack up
Another feature to consider is the via stack. If we go back to the layer stack up discussed previously, we could create the upper and lower portions of the board (see Fig. 2 and Fig. 3) as sub-assemblies that could be drilled and plated individually. This would allow us to then use blind vias from the top layer down to the first high-speed signal layer. However, it is worth noting that once all these layers have been laminated together with the pre-preg material in the center, the resulting layer will be quite difficult to access and will need to be drilled and plated. This will also add significant cost to the overall design. As such, the most cost-effective way to design this board will be to adopt the use of through-hole vias. Through-hole vias will go through the layer stack completely and bring out an annulus on each copper layer.
A common challenge with the through-hole vias arrangement is when we route from a top layer to the second signal layer and there is a via stub left-over that adds parasitic resistance to the signal. What this means is that, if we were to draw a single-ended signal, it would cause a parasitic capacitance to the AC ground that could be as high as half a pico-farad (pF), but the actual value would be determined by the physical characteristics of the via. Whatever the output value, this can have a significant effect on the signal integrity. To effectively maximize the through-hole vias for high-speed design, the solution is to back-drill the via barrel to remove it. To do this, we need to use a drill that is slightly larger than the barrel in diameter and drill the material out. The drill doesn’t need to be done with any difficult or technology-intensive equipment. Rather, this is done by simply using all the through-holes via the most cost-effective approach and then drilling the necessary vias in the back.
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