Test Out and Validate High-Speed Designs with Signal Integrity Simulation

November 20, 2018 Altium Designer

Altium Signal Integrity Simulator waveforms

 

Sometimes the biggest onion can’t be peeled. It seems simple enough. You pick up an onion, a knife, and get going. It would be nice if all of life were so simple, and I suppose it is if you can just break each task into a simple series of steps. Along with intuitive tools, each step leads to the next and pretty soon you’re sending commands from your smart phone to your food processor before you get home.

 

Signal integrity simulators feel like a big unpeeled onion to me. Staring at schematics to determine high-speed signal design considerations is complicated. Years of study have led to application of solid PCB layout techniques for good grounding schemes, careful arrangement of layer stackup, material selection and impedance control, via placement, and termination circuits. All are important in getting PCB layouts accurately designed for signal integrity before fabrication and eventual bring up at the bench.  

 

Signal integrity is usually discovered after fabrication when assemblies are powered on at the bench, or worse, during EMI testing. Many of us have learned the hard way that each and every design detail has great impact on high-speed signals traveling along your energized PCB. It is not enough to choose the latest and greatest high-bandwidth parts if you can’t get the bits to the memory without corruption. Many a network analyzer has demonstrated the importance of careful planning when laying down nets. Wouldn’t it be nice to simulate your nets before you go to fabricate?

Cryptic Simulator Tools are Worse Than Network Analyzers

PCB layout tools have long attempted to provide simulators for signal integrity analysis. The trouble is that the environment adds complexity to the already troublesome world of PCB software tools. Tool development time has concentrated on difficult translations just to produce accurate component and footprint models, and to link vital dimensioning functions with ECAD and MCAD teams. Schematic capture tools have needed time to get the very complicated basics worked out.

 

Network analyzers get you signal integrity results after the fac

Signal integrity simulators are welcome evaluators in EDA tools

 

Rather than miss the opportunity to provide signal integrity modeling, software vendors have tossed ill-conceived simulators into products hoping they will be adopted. Unfortunately, the smart people who would benefit from such tools have given up spinning their wheels with confusing environments and gone back to their labs, where network analyzers can do the same job in a much shorter period of time. I’m sure they’d be thrilled to have a tool that could analyze their designs for signal integrity before boards are built. It just has to work well before anybody uses it.

Confusing Simulator Menus Take Time to Decode

Ever willing to evolve skill sets and adopt newer and better processes, engineers step out of the lab and try to get the simulators going. Optimism turns to frustration when commands to simulate turn into error messages that make no sense. Rather than having clear steps in the tool that port to design development, the simulator communicates syntax errors. Syntax error decoding leads to hours of work, stepping through each message and pretty soon the analysis at hand is lost to another day.

 

Rather than getting signal results the analysis leads to debugging command structures in the software. Realizing time is running out, the boards are sent for fabrication and the archaic design cycle continues. Without signal integrity simulations, the designer is left to trust good analysis techniques for the design. Results will be known when the boards get back and can be powered on in the lab.

IBIS Models Give Framework for Simulator Nodal Behavior

Waiting for fabricated boards before final signal integrity results is a thing of the past with intelligently-built PCB software tools. Rather than complicate the design process with cryptic commands, a unified simulation environment provides the structure necessary to test nets for signal integrity. Only intelligent tools know the power of providing IBIS models to components for modeling parasitic contributions to nets.

 

Altium’s Signal Integrity Model Editor

Use IBIS models to set the framework for signal integrity analysis

 

Simulating signal integrity in a mixed signal design requires a framework that not only models component parasitics but also models power pins. Injection of test signals to test each node requires knowledge of each pin’s operating range to set up sweeps for all possible conditions. Sweeping from least to worst case in busy signal environments is a challenge that results in focus on the integrity of the signal. There is no need to spend time on underlying conditions when the software is smart and unifies all design functionality automatically.

 

When working through the verification and validation process in your PCB design, performance and test methods matter. After all, what good is the verification of a simulation model if the data shows that it doesn’t have the performance for the device you expect to make? The validation process in your PCB design should take into account the device you’re trying to produce into as well as reliable simulation models that provide accurate data and a reference design.

 

Altium Designer offers an intelligent signal integrity simulation tool for your high-speed circuits. The tool is available in both schematic capture and PCB layout, allowing circuit designers insight into termination circuits and their effect on signal integrity early in the design process. Once materials and net dimensions are specified in PCB layout, the tool can be run again to simulate for crosstalk using actual material qualities and net dimensions in the analysis.  

 

With Altium’s unified system, you start designing for signal integrity at first concept. Nets are labeled during schematic capture defining them for use by the simulator when it is time to analyze. Matching impedances are calculated in the Layer Stack Manager after materials are specified for the board. Finally, IBIS models are located in component models, setting up the framework for signal integrity simulation.

 

Let Altium Designer remove the outer layers of your design process and get you to the root of your signal integrity needs. If you’d like to know more talk to an Altium expert.

About the Author

Altium Designer

PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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