A Brief Study of Stubs on a PCIe Connector
Stubs are an important topic in high-speed PCB design, and there is a longstanding guideline that stubs should always be removed from all vias on high-speed digital interconnects. While stubs are bad for high-speed lines, they do not always need to be removed. What is more important is to predict the loss profile and frequencies, and to floorplan appropriately to try and prevent such losses.
In this article, I’ll look at some simulation results with PCIe routing on a high-speed PCB using the example MiniPC project that comes packaged in Altium Designer. The simulation in question will involve calculating S-parameters for PCIe lanes coming off a connector. Looking at these simulation results should help unfamiliar designers better understand how stubs on via and connector transitions influence signal integrity from a simulation perspective, which can help you make the right component selection, placement, and routing choices.
Potential Problems With Stubs and PCIe Routing
In PCIe routing, lanes are routed as differential pairs with AC coupling capacitors. It is typical to route these differential pairs through a connector to reach a peripheral, such as an expansion card. In the process of routing through these expansion slot connectors, there may be some leftover stub on the line that can limit the maximum bandwidth. This can be evaluated in simulation to get very accurate results and to pinpoint the exact bandwidth of a PCIe channel.
Stubs on any high speed transmission line can create losses or reflections as they can act like high frequency impedance transformers on a PCIe lane. Read more about stub analysis in this article.
Although it’s recommended to limit stubs on a PCIe lane, they might be present on the connector used to route into an add-in card or module. As an example, the edge connector used for a vertically-mounted PCIe add-in card might be a through-hole component, and those stubs can play a role in limiting usable signal bandwidth when routing on the same layer as the connector. Routing on the opposite layer may be preferable, particularly when considering placement of capacitor.
An Example With Connector Stub Losses in a PCIe Lane
Because of the interference effects known to occur when a signal traverses a via stub, as well as the need for capacitors to remove DC offset along a PCIe lane, it is worth studying the extent to which via stubs can affect losses when routing through a connector.
The MiniPC board in question uses an Arria 10 FPGA with a PCIe interface, which is routed to a slot connector, as shown below.
The other important specifications we need to know for analysis below are the board thickness and dielectric constant:
- Board thickness = 2.028 mm
- Dk = 3.6 on all layers
Although the layout was not created with an FPGA that has the newest PCIe generation, we’ll evaluate losses in these channels by comparing with the bandwidth requirements in different PCIe generations.
Initial Simulation Results
Insertion loss simulation results for the Tx nets were captured using Ansys SIwave; these results are shown below. To get the board into Ansys SIwave, we used the EDB Exporter utility inside Altium Designer. In the results below, we see a dip right around 14-15 GHz reaching as low as -25 dB, and then recovering back to lower loss levels at higher frequencies.
How do we know that this extreme loss is due to a stub? Simply looking at the graph does not prove the problem is caused by stubs, but there are two good reasons to conclude that this may be a stub:
- If you calculate the first quarter wavelength resonance in these stubs, you’ll find that the first dip would be expected at about 13 GHz. That’s pretty close to the 14-15 GHz resonances seen above.
- The loss profile around 14-15 GHz has narrow bandwidth, which is exactly what you would expect from destructive interference in a moderate-Q resonator.
- All the curves have the typical shape of an insertion loss plot that presents stub behavior, and all of the nets being considered have stubs in the PCB layout.
The dip in this graph limits the data transfer rate to any value corresponding to a Nyquist frequency of approximately 8 GHz (or 16 Gbps for 2-level/NRZ signaling). This would be fine for PCIe Gen4 but not Gen5. If we wanted to totally eliminate this loss or re-use this design with a Gen5 interface, then the layout would need to be modified.
Further Investigation and Changes
Some options for changing the layout include:
- Route the connector pins to the capacitors on the back layer through vias: Although there are some extra via transitions, the connection would come off the back layer and through vias into the caps, effectively eliminating the stubs without back drilling.
- Replace the connector with an SMD equivalent: This would totally eliminate the stubs without requiring two layer transitions through the connector pins and vias. This is also the simplest solution as it does not require any component swaps, although it does require some re-routing.
- Backdrill all stubs: This requires some additional costs and will leave a small amount of stub leftover (usually about 10 mil), so it’s best used when stubs are very long.
If the layout is already complete, #1 and #2 are usually the best options as they could require the least amount of rework, although #2 will depend on what is in the lower layers. For option #1, here is an example connector with SMD mounting. #3 is appropriate if you are willing to pay the costs of controlled-depth drilling during fabrication.
One might expect this type of behavior, where a signal integrity problem like high loss or high reflection is observed around specific frequencies, may come from stubs that resonate strongly when excited. To evaluate why this might happen in a differential channel, one needs to calculate the set of structural resonances in the via stub structure. A guide showing how this is done can be found in the video below.
When you need to evaluate your design in a comprehensive simulation-driven workflow, use the complete set of PCB design, layout, and simulation features in Altium Designer®. When you need to examine signal integrity problems and extract S-parameters from your systems, you can use the EDB Exporter extension to import a design into Ansys field solvers and perform a range of SI/PI simulations. When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects.
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