Microstrip Ground Clearance Part 2: How Clearance Affects Losses
In a previous article, I provided a discussion and some simulation results on the necessary clearance between impedance controlled traces and nearby grounded copper pour. What we found was that, once the spacing between the pour and the trace becomes too small, the trace becomes an impedance-controlled coplanar waveguide (with or without ground). We also saw that the 3W rule for the spacing between the trace and the grounded copper pour is a bit overly conservatice.
Essentially, if your goal is to hit a target impedance, and you’re worried about how nearby pour might affect impedance, you can get closer than the limits set by the 3W rule. However, the exact limit of clearance you can apply depends on the thickness of the dielectric; thicker substrates allow a smaller clearance-to-width ratio, all of which were found to comfortably violate the 3W rule for practical laminate thicknesses investigated in some simulations.
Although we focused on impedance in the previous article, one would rightfully ask, what are the effects on losses? If the reason for this question isn’t obvious, or if you’re not up-to-date on the finer points of transmission line design, then keep reading to see how nearby ground pour can affect losses in impedance-controlled interconnects.
Why Would Ground Near a Trace Affect Losses?
This is a reasonable question, and it relates to how a nearby conductor can modify the electromagnetic field distribution around a trace that carries some static charge or current density. To see how losses might arise when grounded copper pour is placed near a microstrip or stripline, let’s look at the electric field.
In the image below, I’ve drawn out a rough sketch of the electric field around a microstrip. When there is some nearby grounded copper pour on the same layer as the trace, some electric field lines terminate at the edge of the conductor.
Because the ground pour pulls the field lines in towards the ground region, the electromagnetic field is strongly concentrated in the region between the trace and the nearby copper pour. You might be wondering, how does this lead to greater losses?
Skin Effect and Image Current
Now it’s time for a little electromagnetics lesson… When a signal is traveling along a trace, its associated current density will cluster around the edge of the trace that is guiding the signal. However, the typical picture that we all learn in electromagnetics classes only applies when we consider an infinitely long wire that is isolated from all other media, including any other nearby conductors. The reality is that, when a conductor is brought near the trace, the current crowds around regions of the trace where the orthogonally oriented electric field is most intense, which is along the lateral edges of the trace.
In my recent presentations at some conferences, and in presentations I’ve seen from many other researchers, analytical calculations involving the skin effect are presented while ignoring the image current in nearby ground planes and copper pour. This is largely a simplification for calculation’s sake, and for brevity during a presentation. Calculating this particular distribution for every trace arrangement is worth its own journal article in the likes of IEEE or JPIER. However, it’s the major consideration for understanding the role of coupling capacitance and its effects on losses.
To read more about creation of an image current in conductor and how it distorts the skin effect, take a look at this article published in IEEE:
- Moongilan, D. E. C. E. E. N. A. "Skin-effect modeling of image plane techniques for radiated emissions from PCB traces." In IEEE 1997, EMC, Austin Style. IEEE 1997 International Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No. 97CH36113), pp. 308-313. IEEE, 1997.
Because the current crowds up against the edge of a trace, this increases the strength of the interaction between the current and the rough wall of the copper trace. Remember, copper roughness increases the magnitude of the skin effect and creates additional lossy impedance. Now, to see what happens in this interaction, we have to understand how copper plating materials influence losses.
Avoid ENIG, Prefer Silver
John Coonrod has provided some excellent data that shows the effects of ENIG plating progressively higher frequencies in a grounded coplanar waveguide (very similar to a coplanar microstrip with ground) and a lone microstrip with no copper pour. I encourage readers to take a look at one of his YouTube videos at this link. More comprehensive evaluation can be found in this video. In short, John’s data shows that ENIG plating is the primary reason we have greater total losses when a trace is in a coplanar arrangement vs. a simple microstrip. One would reasonably expect similar results for striplines.
The image below shows the important graph from the video I’ve linked above. Essentially, due to the plating bond between copper and nickel, the roughness encountered by the propagating current is much larger in a coplanar waveguide than for a microstrip. Meanwhile, for bare copper, we see very similar losses in both transmission lines. Below a few GHz, there appears to be no difference between the losses in each type of transmission line.
So should you use grounded copper pour near your interconnects, or should you omit it? Obviously, there is more to consider than just shielding, impedance, and losses. Thermal transport is also cited as one reason to place copper pour around a PCB. If you do want to use copper pour around high speed impedance-controlled traces, make sure to test your interconnects with some basic measurements (TDR or S-parameters). The above results should illustrate why immersion silver is often the plating of choice for high frequency/high speed impedance controlled interconnects rather than ENIG.
To be fair, there are some disadvantages to indiscriminately filling copper pour into every signal layer, some of which we’ve noted here. Kella Knack also notes a few disadvantages of copper pour in another article; I would disagree with an implication that using copper pour is a bad design practice and should never be used, but you should consider the drawbacks for your specific design, and be sure to test prototypes based on these assumed drawbacks. The application of copper pour can be used properly or improperly, and its use is sometimes framed as one of those “always” or “never” type of choices; both sides are probably taking each other’s design choices out of context. In any case, you do need copper pour to define PCB elements in modern RF designs that provide shielding, substrate-integrated waveguides, and impedance-controlled coplanar waveguides. Make sure to use it wisely and apply the appropriate plating if losses will be problematic.
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