Power Integrity Analysis in Your PCB Design Software

Zachariah Peterson
|  Created: November 11, 2022
Power Integrity Analysis in Your PCB Design Software

Power integrity problems can abound in modern PCBs, especially high-speed boards that run with fast edge rates. These systems require precise design of the PDN impedance to ensure stable power is always delivered throughout the system. Without carefully considering the PDN impedance, you’re at risk of creating ripple and noise in the power distribution network when fast signals switch states. As more signals switch in large ICs, the result is the potential for greater power instability and system disruptions during operation.

Some designers might wonder what is power integrity analysis: it’s a set of methods for understanding how your components draw power and how the structure of the board affects stable power delivery. Altium Designer offers some important tools for power integrity analysis, including the new Power Analyzer extension from Keysight. This article will give an overview on how to perform power integrity analysis in a PCB, as well as where to access these features in Altium Designer.

Power Integrity Challenges in DC and AC

Some products will operate at high voltage, high speed, high current, high frequency, or all of the above, and they can experience a range of signal integrity and power integrity problems during operation. Power integrity analysis aims to identify operation problems from two perspectives: DC and AC. Furthermore, power integrity analysis can be performed in two phases: in the schematic and in the PCB layout. Simulation experts are sometimes called in to evaluate a design prior to prototyping or production in order to identify potential power integrity problems in DC and AC domains.

Power integrity analysis involves analyzing the structure and electrical behavior of the PDN in a PCB. To be more specific, it involves calculating certain electrical quantities which can be indicative of power integrity problems. In particular, there are several quantities that can be calculated in the PDN using simulation tools, which can then be linked to certain power integrity problems that would be observed in a PCB during operation. Quantities to calculate include (but not limited to):

  • PDN Z-parameters (self-impedance and transfer impedance) in AC and DC, or S-parameters
  • DC resistance and current density in rails and planes
  • Voltage and current distribution throughout the PCB layout
  • Transient response on power rails observed in the time domain

These important mathematical quantities in power integrity analysis can be calculated in schematics using SPICE or IBIS models, or they can be calculated in the PCB using an electromagnetic field solver. After calculating the quantities of interest, they should be compared to target values to 

What Power Integrity Problems Can Occur in a PCB?

There are several power integrity problems that can occur in a PCB, all of which are related to the list of quantities listed above. Some of the common power integrity problems that can occur in a circuit board include:

  • Large power rail collapse (ripple, seen as a transient response) and ground bounce
  • Radiated emissions due to weak decoupling and ripple
  • Noise coupling between different regions of a PCB
  • Excessive power dissipation that produces heat

The goal in constructing a PDN is to ensure the power drawn into the components on a PCB is delivered with minimal instability. Some of the power integrity problems listed above are observed as signal integrity problems (specifically ground bounce) and EMI/EMC problems (noise coupling and emissions). The matrix below shows which power integrity problems are linked to the mathematical quantities listed above.

 

PDN self impedance

PDN transfer impedance

DC resistance

Power rail ripple

High PDN impedance

N/A

N/A

Excessive heat dissipation or power loss

N/A

N/A

High DC resistance

Ground bounce

Lack of small bypass capacitors, or excessive inductance

N/A

N/A

Radiated emissions

Excessive power rail ripple (see above)

N/A

N/A

Ripple observed between ports

N/A

Low PDN transfer impednace

N/A


To learn more about these factors in a PDN and how they affect stability in power delivery, read the following resources to fully understand power integrity analysis.

Power Integrity in Schematics

Schematics are a good place to start modeling AC power integrity in a PCB layout. In this domain, it's possible to use SPICE simulations or IBIS-based simulations to model your decoupling strategy and determine whether your idealized PCB layout can support stable power delivery, particularly for fast digital integrated circuits.

Schematic-level power integrity does not account for the important physical factors in a PCB layout that will impact power integrity. Instead, investigating power integrity in schematics helps a designer develop design goals for the PDN to ensure power delivery will be as stable as possible. This requires modeling the PDN response using generic components to represent the physical aspects of the PCB layout. Some of these physical aspects include:

  • Decoupling/bypass capacitor models, which includes ESR and ESL values
  • Plane capacitance, which is typically on the order of pF
  • Spreading inductance, or the inductance of the region where current exists in power/ground plane layers
  • Via inductance, although this is normally included in the decoupling/bypass capacitor models
  • Topology with multiple rails in the PDN
  • A switching element that simulates a bitstream so that a periodic transient response can be observed

A relatively simple model that includes only RLC elements is shown in the example schematic sheet below. This example can be used to estimate PDN impedance and the inductive slope in the PDN impedance spectrum out to several hundred MHz. The model can also be used to directly visualize ripple on the PDN by running a transient analysis simulation.

Power integrity analysis schematics

The above series RLC circuit blocks are being used to model a decoupling capacitor network that might be placed in the board. The lower section shows the connections between the plane layers and a component package. Finally, the transistor is used with a pulsed source to model current drawn into the network. The current and voltage measurments at the output points can be used to determine the PDN impedance using Ohm's law.

Any of the standard methodologies in a SPICE simulation (sensitivity, Monte-Carlo, impulse response determination, etc.). Based on these results, it's possible to determine target values for your RLC elements in your SPICE model. The primary physical aspect this determines is the plane capacitance, as well as the number of decoupling capacitors. More information can be determined once the PCB layout is completed and ready for evaluation.

DC Power Integrity in the PCB Layout

The DC resistance in a circuit board depends on the dimensions of your power plane and interconnects, and it’s the starting point for understanding power integrity. Once this aspect of a circuit board is addressed, a designer can take steps to ensure they meet target impedance goals to prevent signal integrity problems that arise from unstable power delivery.

DC power analysis starts in the PCB layout and requires setting up a simulation that maps power distribution throughout different power nets in the PCB layout. This is represented visually as a tree with different power levels, which maps power flow from a top-level input and down to the device level. The newest power integrity analysis extension in Altium Designer is the Power Analyzer by Keysight. This utility can set up a power tree based on your netlist and project information. An example power tree is shown below.

PDN power tree

 

Once this power tree is set up, it can be used to determine the DC resistance in the PDN. The image below shows an example output from Power Analyzer in Altium Designer. This extension provides power integrity calculations inside the PCB Editor in Altium Designer, and the results are checked against design goals or constraints automatically. No additional analysis tools are needed to implement this calculation, and the results do not need to be checked manually against your design rules.

The results below shows DC current displayed as a heat map in a large trace leading between two vias. In particular, the tool shows that the calculated current in the attached vias is 1.785 A. Based on operational goals in the design and operating current limits defined in IPC standards, it is possible to determine whether any modification of the design is needed. After making modifications, the simulation can be immediately re-run and the results can be examined to determine when any of the identified problems have been solved.

Power Analyzer Keysight

 

If we zoom out from individual traces or rails, it's possible to see current distribution throughout a plane layer or along large interconnects. Multiple points on a power rail can be selected and examined for voltage drop or current density, all being visualized as a heatmap. This view provides a simple way to determine when the DC resistance of a net becomes too large or when there is a current bottleneck that produces a hotspot.

Power integrity analysis GIF

 

AC Power Integrity Analysis for High-Speed Design

High-speed PCBs rely on exact transmission line impedance to ensure the design will operate correctly, but they also require very low power delivery network impedance. Circuit boards for high-speed digital systems are designed with a target impedance in mind. The PCB stackup, selected decoupling capacitors, and PCB laminate thickness combines to determine the impedance of the PDN, which is intended to be designed to meet a target impedance spectrum.

Keeping the PDN impedance low is important for ensuring high-speed components do not create power rail ripple and ground bounce when they switch. If the PDN impedance is low enough, then these effects will not be noticed in the system. Once the plane impedance in the PDN has been calculated, it’s now possible to determine whether any power rail ripple and noise will cause the power delivery to fall outside the allowed limits.

To help you succeed in power integrity analysis, the Power Analyzer by Keysight and the existing simulation tools in Altium Designer® can help you get started evaluating your board's functionality. As new capabilities come available, expect more updates to the Power Analyzer extension, including AC power integrity analysis direclty in the PCB Editor. Keep an eye on the What's New page to keep track of new feature releases in Altium Designer.

PCB impedance control

 

Altium is committed to continuously bringing you the best tools for power integrity analysis, all operating within schematic and the PCB layout. As these capabilities are built into the application, more advanced power integrity simulations will become accessible inside the PCB Editor. In addiiton to improvements in the PCB Editor, additional capabilities will be made available to collaborators through the Altium 365 platform.

We have only scratched the surface of what’s possible with Altium Designer on Altium 365. Start your free trial of Altium Designer + Altium 365 today.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2000+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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