Ruminating Rigid Flex - Part 3

Ben Jordan
|  Created: February 21, 2017  |  Updated: December 11, 2020

In this third installment of the blog series on Rigid-Flex design, I discuss a few of the documentation requirements needed to get a flex or rigid-flex circuit board fabricated. Along with that, there are a few flex-circuit related issues to watch out for.

Fab documentation for flex circuits and rigid-flex boards.

In the last blog on rigid-flex PCBs, I talked about the fabrication processes typically used by board houses. It’s important to understand the steps required to build up a rigid-flex or flex circuit PCB because it has a big effect on how you need to design the board. And it also affects what needs to be included in your fabrication data set to send the design to successful fabrication. If you haven’t read 1 and 2 of this blog, go read them here and here before continuing on.


Let’s talk about documentation then. This is essentially where we tell the fabricator what we want, and it’s probably the most likely part of the process where errors or misunderstandings can make costly delays happen. Fortunately, there are standards we can reference to make sure we are communicating clearly to the fabricator, in particular IPC-2223B (which I am referencing in writing this).

It could boil down to a few golden rules:

  1. Make sure your fabricator is capable of building your rigid-flex design.
  2. Make sure they collaborate with you on designing your layer stack to fit their particular processes.
  3. Use IPC-2223 as your point of reference for design, making sure the fabricator uses the same & related IPC standards -  so they are using the same terminology as you.
  4. Involve them as early as possible in the process.

Output Data Set

In interviewing a handful of rigid-flex capable board houses locally, we found that many designers still present gerber files to the board house. However, ODB++ v7.0 or later is preferred, since it has specific layer types added to the job matrix that enable clear flex- documentation for GenFlex® and similar CAM tools. A subset of the data included is shown in table 1.

Table 1: Subset of Layer Types in ODB++ (v7.0 and later) used for GenFlex

(Source: ODB++ v7.0 Specification)

Layer Type

Base Type




Clearances of a coverlay layer



Clearances of a covercoat layer



Pattern for die-punching of the flex



Shapes and locations of stiffeners to be adhered

Bend Area


Labelling of areas that will be bent while in use



Pressure Sensitive Adhesive shapes and locations



An area definition (Rigid, Flex, or arbitrary)

Exposed Area


An exposed area of an inner layer and it’s associated coverlay (could also be used for embedded components)

Signal Flex


A signal layer for a flex

Power Ground Flex


A power of ground layer for a flex

Mixed Flex


Mixed layer for a flex



A mask for defining which areas within a layer should be masked off from plating process



A mask for defining which areas within a layer should be masked off for immersion gold

There are some issues we face if using Gerber for the output data set, or earlier versions of ODB++. Namely, the fabricator will need separate route tool paths and die cut patterns for each rigid and flex section in the layer stack. Effectively, mechanical layer films would need to be produced to show where voids need to be in the rigid areas, and more to show where coverlay or covercoat will be on the exposed flex areas. The coverlay or covercoat also has to be considered a mask for component pads for those components that may be mounted on flex areas.

In addition, careful attention needs to be paid to layer pairs for drilling and through-hole plating, because blind vias from a rigid surface layer down to an opposing flex- layer will have to be back-drilled and add significant cost and lower yield to the fab process.

As a designer, the question is really then, how can I define these areas, layers and stacks?

Define the stack by area using a table

The most important documentation you can provide your fabricator is arguably the layer stack design. Along with this, if you’re doing rigid-flex, you have to provide different stacks for different areas, and somehow mark those very clearly. A simple way to do this is make a copy of your board outline on a mechanical layer, and lay down a layer stack table or diagram with a pattern-fill legend for the regions containing the different layer stacks. An example of this is shown in figure 1.

Figure 1: An example of a stack diagram showing fill patterns for rigid and flex areas.

In this example, I used the matching fill patterns for different stack areas to indicate which stackup layers are included in the Flexible part or the Rigid part. You can see here the layer item I named “Dielectric 1” is actually an FR-4 core, which could alternatively be considered a stiffener.

This poses a new problem, in that you also have to define in 2D space where bends and folds can be, and where you will allow components and other critical objects to cross the boundaries of rigid and flexible sections. I will discuss this a little more later on.

Conveying the PCB design intent

We all know a picture is worth a thousand words. If you can generate a 3D image showing flexible and rigid areas this will help the fabricator understand your intent more clearly. Many people do this currently with the MCAD software, after having imported the STEP model from the PCB design. Figure 2 is an example of this concept.

Figure 2: Bending up the mechanical model to show design intent.

This of course can have the added benefit of detecting flex to flex and flex to rigid interferences ahead of epic failure.


You can see also from the image above, that rigid-flex designs imply that components might exist in layers other than top and bottom. This is a bit tricky in the PCB design software, because normally components must exist on top or bottom. So we need some ability to place components on inner layers.

Interestingly, Altium Designer® has always supported pad objects on any layer, so this is not impossible. There’s also an implication that silkscreen could exist on flex layers as well. This is not a problem, since coverlay material can adhere well to the silkscreen ink. The trick is more to make sure there’s adequate contrast for the color of ink chosen against the coverlay material. Also, resolution is affected since the ink has to traverse a small gap beyond the screen to land on the flex coverlay. Again, this is something that needs to be discussed with the fabricator to determine what’s possible and economical.

Side note: If you’re going to the effort of drawing the regions of the PCB which are exposed flex layers, and placing components on those regions, this also makes a reasonable method for placing embedded components into cutout regions of the board. You need to generate a set of very clear documents that show where the cutouts are and in which sections of the layer stack they apply. This is going to be limited depending on the fabricators methods - either back-drilling or multiple laminated stack-ups can be used. So communicating your intent and minimizing the number of separate cutout stack sections is important. It’s best to completely avoid having intersecting cutouts from opposite sides of the board.

Side-note: Defining Flex Cutout

Notice in figure 1 how there are no hard corners, but rather there’s a minimum radius to each angle? IPC recommends greater radii than 1.5mm (about 60 mils), to reduce the risk of tearing of the flex at corners. The same goes for slots and slits in the flex - make sure there’s a designed-in relief hole at each end of diameter 3mm (⅛”) or more. Another example of this is shown below.

Figure 3: Slots, slits and inside corners should have tear-relief holes or tangent curves with minimum 1.5mm radius.

In order to produce reliable rigid-flex based products, there are many considerations relating the fabrication and the end-use of the flex , to the design of the copper pattern. In the next blog I discuss several of these do’s and don’ts of Rigid-Flex

About Author

About Author

Ben is a Computer Systems and PCB Engineer with over 20 years of experience in embedded systems, FPGA, and PCB design. He is an avid tinkerer and is passionate about the creation of electronic devices of all kinds. Ben holds a Bachelor of Engineering (CompSysEng) with First Class Honors from the University of Southern Queensland and is currently Director of Community Tools and Content.

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