# A Short Tour Through The PCB Design Process

Kella Knack
|  Created: October 17, 2020  |  Updated: March 16, 2021

In several previous articles, I have addressed the PCB design process in terms of the tools involved, the basics of electromagnetic behavior on transmission lines, signal integrity, power delivery design and numerous other PCB design-related topics. But, one of the most important basics is to have a good sense of the factors that are considered to have the fastest design flow. This info spans the buses and types of signals including operating frequency and termination types; Vdd voltages; the impedance of each Vdd rail, selection of the DC to DC converters, calculating the number and values of bypass capacitors and creating schematics of these elements that become part of the overall schematic set that is delivered to the board manufacturer.

The basis of this process is drawn from the many years of experience we have had in designing hundreds of PCBs ranging from PC motherboards to switch fabrics for terabit routers, and all sorts of products in between. This article is presented in the specific steps that comprise the process and help to ensure that the final product build will match the as-designed board.

## The Steps

Just as it is necessary to have a complete plan and set of specifications to build a house properly, the design of a PCB product consists of numerous steps with specific details. The specific steps of this process are as follows:

### Step 1 — Building a Block Diagram

A block diagram includes all of the buses and other signals types. To build a comprehensive block diagram the following elements must be shown:

• The quantity of signals in each bus.
• The technology for each bus
• Its operating frequency.
• Its termination type.

The completed block diagram, provided as an example in Figure 1, becomes page 1 of the schematic set.

Figure 1. Page 1 of a Typical Schematic Showing a Block Diagram

### Step 2 — Listing All of the Vdd Voltages

The Vdd voltages information includes:

• The ICs they supply
• The calculation of the peak current for each voltage and allowable ripple.
• Allowable ripple is calculated by consulting each IC datasheet.
• For those ICs that have single-ended CMOS output drivers, the maximum allowable ripple will be determined by taking the noise margin for the inputs and assigning part of the noise margin to ripple, crosstalk, Vdd/Ground bounce and reflections.
• The previous numbers come from the noise margin analysis part of the design rule creation process that is detailed in Reference 1 at the end of this article.

As noted in earlier articles, many applications notes specify ferrite beads in the power leads of various circuits such as SERDES and phase-locked loops (PLLs). These beads are usually called out “because we have always done it this way.” As noted in my article on this topic, the correct approach is to connect all power leads of the same voltage to a single voltage rail and not add ferrite beads which can degrade the performance of the board.

### Step 3 — Calculate the Impedance of Each Vdd Rail

The impedance of each Vdd rail is obtained by dividing the max ripple by the maximum delta I. This will be the target impedance of the overall PDS for that voltage.

Note: Often, it is not possible to obtain maximum delta I information from component vendors. In such cases, the only safe thing to do is assume that the maximum delta I swings from zero current to peak current.

### Step 4 — Selecting the DC to DC Converters

This step incorporates the following information:

• The DC-DC converters supply the maximum I and have an output impedance that meets the target impedance calculated in Step 3 noted above.
• DC-DC converters can be either switch mode or linear for any supply.
• Switch-mode supplies will always be more efficient.
• When application notes call out linear regulators only, as often happens on FPGAs, this is because the authors do not know how to suppress the switching transients that often appear at the outputs of such regulators when incorrect capacitors are chosen. The methods in this document take care of this so that linear supplies are not required.

### Step 5 — Building The Block Diagram of the PDS

The block diagram of the power delivery system, which is shown in Figure 2, becomes page 2 of the schematic set.

Figure 2. Page 2 of a Typical Schematic Showing the Power Delivery System

### Step 6 — Calculating the Number and Value of the Bypass Capacitors

This step involves calculating the number and value of the bypass capacitors required to meet the target impedance that has been calculated in Step 3 above. This involves covering the frequency range from where the DC-DC converters cease to regulate to at least 100 MHz. This frequency range was chosen knowing that processor cores and network processor cores are likely to go from standby current to active current at any rate in that range depending on traffic. There are several tools available for this step, including the PDN_Tool_V10 available from the Altera web site. Note: This tool is now called the Intel PDN Tool 2.0. It’s essential to use lossy ceramic capacitors such as X7R or X5R to ensure no unwanted resonances appear in the PDS.

### Step 7 — Creating a Capacitor Page

This step involves creating a capacitor page for all of the capacitors that result from the calculations performed in Step 6. This page becomes page 3 of the schematic set. It’s crucial to not scatter bypass capacitors around the various sheets of the schematic next to components as this practice makes it difficult to determine how many and what kind of capacitors are in the PDS. Further, scattering capacitors throughout the schematic does not add any value to the design. While some applications notes may specify placing capacitors next to components with instructions such as “as close as possible” and also specify arbitrary numbers of capacitors this advice has been proven to be invalid. The capacitor usage instructions in applications notes should be ignored, and the procedures spelled out in the PDN design methods described in Reference 1 should be followed. The final capacitor page is shown in Figure 3.

Figure 3. A Typical Bypass Capacitor Array in a Schematic

### Step 8 — Determining the Plane Capacitance

Here, the plane capacitance required for each of the supply voltages from step 2 is determined. This calculation is not as straightforward as that used to determine the discrete capacitor population. The voltages that need the most plane capacitance are those that supply wide, single-ended data buses. A method for calculating the approximate amount of plane capacitance needed is described in Reference 1 on page 171. This equation has proven to be conservative but reliable.

### Step 9 — Building the Primary PCB Stackup

It’s important to provide enough plane pairs to create the interplane capacitance calculated in Step 8 and to provide enough signal layers to contain the expected wire load. A typical stackup drawing is shown in Figure 4.

Figure 4. A Typical PCB Stackup

## Steps 10 to 12 Are Comprised of the Following:

### Step 10:

Performing noise margin analysis on each logic type in the block diagram for crosstalk, reflection, Vdd/ground bounce and ripple requirements.

### Step 11:

Simulating at least one member of each net type shown in the block diagram to determine termination and sequencing requirements.

### Step 12:

Building the technology table, as shown in Figure 5, that lists the routing, frequency, spacing and termination requirements for each class of nets.

Figure 5. A Typical Technology Table

## Steps 13 to 19 Include the Following:

### Step 13:

Completing the schematic.

### Step 14:

Adding testability features to the schematic such as impedance test traces and plane capacitance access test points.

### Step 15:

Placing the components on the surface of the PCB, assessing the routability and performing the thermal analysis. This includes adjusting the placement and stackup as necessary to meet both sets of needs. In addition, stacking stripes are added along one edge of the PCB to allow checking of the final stackup of the finished PCBs.

### Step 16:

Determining the pad stack dimensions and minimum spacing of holes to ensure there are plane webs between the clearance holes in planes and satisfying insulation requirements, aspect ratio requirements and annular ring requirements.

### Step 17:

Building the drill table and fabrication drawing.

### Step 18:

Routing the PCB using the generated checklist to ensure all steps in the design process have been completed in a satisfactory manner.

### Step 19:

Shipping the artwork to the fabricator.

## Summary

A complete set of process design steps goes a long way in ensuring that all of the information necessary to design and fabricate a board design has been specified for a PCB that will work right the first time as well as throughout the entire product life cycle. This information encompasses all the board features including buses and signals, Vdd voltages and Vdd rail impedances, DC-DC converters and bypass capacitors. The schematics created as a result of this process become part of the delivered schematic set. Following these steps will ensure that the PCB design process is thorough and optimized to be as fast as possible to meet both scheduling and cost requirements.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium.

## References

1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High Speed PCB and System Design,” Volumes 1 and 2.