Should You Use Your PCB Power Plane as a Return Path?
Power planes and ground planes are important for more than just distribution of supplying power. When defining reference planes, both with impedance controlled routing and in managing return paths, your stackup might force return currents to pass into a PCB power plane before being coupled back to a ground layer. Even though you define a GND reference layer as a the basis for your impedance-controlled trace width, you still have to define a clear return path along the length of the power plane in your design. Let’s take a look at some good practices for controlling return paths in your PCB with a power plane as a return path.
Signal Behavior with a PCB Power Plane as a Return Path
When we say "return path," we're referring to the path that is naturally followed by the return current in a design, where by the current can travel back to the low potential terminal at the input side of the PCB. For a signal traveling on a transmission line, the return path is determined by the capacitance between the line and its reference plane. A higher capacitance, higher frequency, or both means that the return current can easily pass into the ground layer as a displacement current.
This, in turn, means that the distance between a transmission line and its reference plane, whatever that type of reference plane happens to be, determines some important electrical behavior in real designs. Such behavior includes:
- EMI susceptibility from external sources, which can be received inductively through a large current loop, or capacitively via the electric field
- Inconsistent impedance, which will arise when routing between plane regions, over gaps, or with varying trace widths along an interconnect
- Crosstalk from other traces, which can more easily couple inductively into a victim trace if the design has a
- Losses during propagation, which occurs due to field line concentration between the transmission line and the nearby reference plane or other conductors
If you can choose between using a power plane or ground plane as the adjacent layer that provides a return path or signal reference, you should always choose the ground plane. There are two reasons for this, which I’ll explain in more detail below.
Before discussing how a power plane does (or doesn't) actually function as any kind of return path, we have to ask the question: how would current from a transmission line get into the power plane to begin with. The answer is: capacitive coupling! Remember, as was mentioned above, the return path is induced between a transmission line and any nearby conductor. For a nearby plane layer, this happens whenever there is a changing electric potential between the line and the plane. Therefore, whenever we have a trace being routed next to a plane, and a digital signal travels along that trace, we now have a displacement current being driven in the plane layer.
If the nearby plane were a ground plane at the same potential as our low potential point at the power input, then everything would be great. The problem with this is, when the current needs to then pass from a power plane and into the nearby ground layer, the current will need to bridge through another dielectric layer to reach a ground plane.
Depending on how the stackup is designed and the area in the board where the signal is induced, the capacitance between the two layers could form a very high impedance path between the power plane and the ground plane. Depending on the stackup, such as the simple 4-layer stackup shown below, the plane capacitance between the power and ground plane layers could be very small (on the order of femtofarads per sq. in.), creating an extremely high impedance return path except for extremely fast digital signals or very high frequency RF signals. The only other option in this journey between the power plane and the ground plane is through the nearest decoupling capacitor, as shown below. In either case, you will have an EMI problem
For a very low-speed signal (such as rise time-limited I2C or SPI signals), this might not be the biggest problem. It certainly won't be a problem with purely DC or low frequency analog. However, with today's standard CMOS components, even low-speed signals in common digital components can have this problem. So what's the solution? The answer is found in redesigning the PCB stackup.
Give Your Multilayer PCB Stackup a Clear Return Path
Like most routing and layout problems, which then create EMI problems, the source of the problem is usually one of defining ground, or having the wrong layer arrangement in the PCB stackup. Although you can use the power plane as an impedance reference and return path for signals, you’ll need to place a nearby ground plane to prevent coupling between layers in the type of layer stack shown below.
One stackup that is sometimes used in denser designs is the 6-layer stackup shown below. The top and bottom signal layers are coupled directly to ground, yet we still have a power plane (in blue on L3) that might have high plane capacitance to ground on L2, depending on layer thicknesses.
An alternative layer arrangement that is not ideal with high speed routing on an internal layer is to have two adjacent signal layers and power on L2. This would allow internal crosstalk and create problems getting the return current back to ground. It also allows switching noise from signal layer 1 (surface layer) to capacitively couple into signal layer 3. A better arrangement would be to use the 6 layer board shown above, or possibly the alternative 4-layer stackups shown in this article.
What about coupling directly into traces? Normally, the parasitic capacitance between the neighboring layers can be quite small due to the small dimensions of signal traces, creating a somewhat high impedance return path between any return current in the power plane on L3 and the ground plane on L5. The normal way to provide a low impedance return path between any return current in the power plane and the ground plane is to place a decoupling/bypass capacitor between the power/ground planes. In the above example, the preferable low-impedance path for any return current induced in the power plane is directly into ground on L2, not on L5.
The Takeaway: Engineer Your Return Path
Whether you allow signals to couple back to the power plane followed by capacitive coupling into the nearest ground plane, or back to the ground plane directly, you’ll need to carefully engineer your return path to prevent undesired coupling between any return signal. The important point here is that any circuit in your board is complete when it connects back to the ground plane, regardless of whether this coupling is direct, through decoupling/bypass capacitors, or thanks to interplane capacitance. This is why, in modern PCBs, we always say to route adjacent to a ground plane: this allows the return path to be sent directly to the ground plane without using bypass caps, stitching vias with copper pour, or other measures that don't solve the problems created by a bad stackup.
While you can technically take advantage of a power plane as a shielding layer and a reference plane (assuming the potential difference between the signal track and the power plane is not 0 V), it becomes difficult to control the return path in general. This is particularly true with high-speed/high-frequency boards. In more advanced designs that run at low signal levels, you might be using differential pairs, in which case the return path is provided by differential driving, i.e., it flows parallel to the HIGH signal trace. If you’re interested in learning more about tracing the return path in your board, take a look at this article from Francesco Poderico.
The newest PCB layout and routing tools in Altium Designer® include a ground return path tool that interfaces with the DRC engine. This allows you to define limits on the deviation between a trace and its nearest reference plane as a design rule. This rule is checked automatically by the interactive routing tools as you create your board. You’ll also have a complete set of tools for analyzing signal integrity and preparing manufacturer deliverables.