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    Understand the AC and DC Return Path on a High-Performance Mixed-Signal PCB

    Francesco Poderico
    |  July 23, 2019

    High performance mixed-signal PCBs are difficult to design. Proper grounding and routing are essential to ensure accurate ADC conversion. In this article we’ll discuss a complex topic; the importance of designing a controlled current path on high performance mixed (Analog/Digital) PCBs, and how this impacts the performance of your board.

    What are we going to learn?

    •    Loop currents follow different path (depends from their frequency range.)

    •    How to design the return path current during the placement phase.

    •    How an ADC is partitioned (inside) and why we have the AGND pin and the DGND pin.

    •    How to prevent digital logic ground to contaminate analog ground.

    How current flows between 2 ICs.

    Understanding the current flow between 2 ICs is very important, because, as we’ll see the return path is not always obvious. The design of return path is vital to avoid pitfall during the partition of our board. 

    Current Loop at Low Frequency

    Let’s start by analyzing the current loop between 2 ICs (IC1 and IC2 figure 1). Let’s assume that IC1 is driving high (from a totem pole output), and let’s examine the current path at low frequency [1,2]. As we can see from figure 1, in DC or at low frequency [1,2], most of the energy comes from the power supply, and the current loop will mostly involve the power supply.


    Figure 1. In this example IC1 is driving high, we can see in blue the expected current loop in DC

     

    Current Loop At High Frequency

    But what is going to happen at high frequency?[1]

    In this case, the situation is going to be different since, during a “fast edge” transition, most of the energy will be provided by the bypass capacitor C1 (and from the power plane). Therefore the new current loop will be as shown in figure 2.


    Figure 2. Current Loop (high frequency) during a transition high -> low bypass capacitor are the source (and sink) for the current.

    By analyzing figure 2, we can already make some consideration:

    • The current loop at high frequency is different from the current loop at low frequency.
    • The position of C1 is a key factor for reducing the current loop shown above and therefore the radiated emission.
    • A solid ground plane should help us to control the return current.

    Let’s examine the same example in a bit more detail, and let’s see how the position of each component (IC1, IC2, Bypass capacitors, Power supply) influences the current loop.

    As a general rule, the return current will follow the minimum impedance path. Which (in simplistic terms) means it will follow the minimum resistor path at low frequency and the minimum inductor path at high frequency.

    To know more about this subject, I highly recommended reading “resistive vs inductive return current path” [1], in which the author proposes an interesting method for determining the frequency range and shows in his example that, for practical circuits, the inductance effect begins to dominate in the range of kHz.

    Now, let’s consider the following example (figure 3). And let’s assume that IC1 and IC2 have only one reference pin (pin 14) and one power pin (pin 16). Let’s assume IC1 is driving and let’s see the current path at low and high frequency.


    Figure 3. IC1 is driving the trace in yellow, we can see all the current paths.

    In figure 3 we can see that in DC, current flows from the power supply through pin 16 (IC1) then through the traces between IC1 and IC2, and then from pin14 (IC2) goes back to the power supply through the minimum resistor path (shortest path).  Let’s examine what is going to happen at high frequency.


    Figure 4. AC current path

    In figure 4 we can see that the AC current path is very different. This is because at high frequency the power source is the bypass capacitor. Since at high frequency the return current tends to pass in the minimum inductor path, (below the trace in case of microstrip.)

    Internal Structure Of A Typical ADC/DAC

    To continue our discussion on mixed-signal design we need to understand the internal structure of a modern ADC/DAC (see figure 5).


    Figure 5. Internal configuration of a modern ADC/DAC

    A modern ADC is internally partitioned in an “analog” section and a “digital” section, same as we normally do on our PCB. This allow the IC designer to maintain the required performance by keeping separate the digital reference from the analog reference, and this is the reason why on most ADC/DAC chip we have an “AGND” and a “DGND” (AGND is the Chip Analog reference while DGND is the chip Digital reference). If we have a look at the figure 5, we can see that there is a small stray capacitor between the digital ground and the analog ground (which unfortunately is not possible to eliminate). This capacitor can cause performance issues if we are not careful (see figure 6). Let’s imagine the DGND point is very noisy. We can model this by adding a noise generator between our ideal ground and the DGND pin. Due to the stray capacitor Cstray, the noise from the DGND pin will degrade the ADC reference causing performance degradation.


    Figure 6. Effect of noise on DGND pin

    By looking at figure 5 and 6 it’s not difficult to understand that for a high-performance ADC/DAC we need:

    1. To minimize the impedance between AGND pin and DGND pin.
    2. To minimize the noise at the DGND pin.

    It is not possible to create rules that work in every situation, however in my own design I achieved the above as follows:

    1. I do not split the GND plane. Instead I try to figure out the return current (discussed earlier).
    2. I treat the ADC/DAC as an analog component…and I connect the “DGND” to the “ANALOG area of my PCB.
    3. For ADC/DAC with a resolution higher than 12 bits, I usually add a digital buffer near the ADC. This is done to minimize the Vnoise on the DGND pin.
    4. I pay a lot of attention to the placement of each bypass capacitor (each power pin has at least one or more bypass capacitor).
    5. Altium offers many resources to all PCB Designers, you may want to read up more about Power Delivery System Design, or talk to an Altium expert today to learn more. 

     

    Suggested reading: 

    Archambeault, Bruce, IEEE® EMC Society Newsletter, Fall 2008, Issue 219, "Part II: Resistive vs. Inductive Return Current Paths"

    Howard W Johnson, Martin Graham High-Speed Digital Design, Prentice Hall PTR

    Elya B. Joffe, Grounds for Grounding: A Circuit to System Handbook, IEEE

    W Kester, J Bryant, M. Myrne, MT-031 Grounding Data Converters and Solving the Mustery of AGND and DGND, Analog Devices

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