When I was much, much younger, I looked at the pin layout on the back of a processor and wondered how anyone can possibly route all of those electrical connections on a PCB. I didn’t know much about signal integrity, of fanouts on PCBs then but fast forward fifteen years and now I get to layout those traces on PCBs.
Fanout is a technique where short traces and vias are used to connect inner rows of pins on high pin-count ICs. Fanout can also route traces to a device with very closely spaced pins. The idea is to make it easier to connect traces and vias to ICs with high pin density and with multiple rows of pins. Small DIP ICs with small pin spacing can be easily accessed using fanout techniques.
In addition to DIP ICs with small form factor, fanout is used in ICs that connect to the PCB using a ball grid array, or BGA. The high pin counts in devices like FPGAs and microcontrollers are difficult to solder manually. Incorporating a BGA in your PCB design makes for easier routing and prevents accidental bridging of neighboring pins during soldering. BGAs have also been shown to be the most cost-effective method for packaging high pin count ICs on PCBs.
PCBs with BGAs allow assemblers to easily connect IC packages with high pin count to the board during assembly. The routing pattern for vias used between the IC pins is called “fanout” and should not be confused with matching between output and input currents in logic ICs. Traces between balls and any required vias between layers must be included in the PCB layout.
Three fanout alignments are traditionally used when routing between IC pins in a BGA. Neighboring vias can be connected diagonally or in an “X” pattern in quadrants. Vias can also be connected diagonally in a clockwise or counterclockwise ring pattern beneath neighboring balls. These methods are sometimes lumped together under the term “dog-bone” fanout.
Certain trace routing principles become more important, depending on the application of your PCB. In BGAs for high pin-density ICs, proper fanout will require densely-packed traces. This increases the risk of crosstalk, especially in high-frequency circuits. The fanned-out traces will most likely be buried, and the board will require more layers to accommodate the high trace density. Vias between layers can be formed using the “via-in-pad” design.
Signal Integrity and Necking
The design rules for high-density BGA fanout are intended to maintain good signal integrity. It is generally a good idea to match the impedance of traces to 50 Ohms for single-ended nets and to 100 Ohms for differential pairs. As pin-density increases, more signal layers will be required to route traces to the BGA.
Setting the typical trace clearance according to conventional design rules can be problematic in BGAs with high pin density. These arrays have tight clearances, and the trace width may need to be adjusted as you route into the BGA. This technique is called “necking.” Obviously, changing the width mid-trace allows you to route the required connections but it can create some signal integrity problems.
Trace density routing to a BGA can be very high
Changing the width mid-trace changes the impedance encountered by signals as they move through a trace. In low-frequency devices with low current, the signal problems that could be created by necking are negligible. In higher frequency devices, this impedance discontinuity creates reflections, changes the scattering parameters, and increases the trace resistance. The effect of reflections becomes especially visible on the timing edges of digital pulses.
Heat generation in high-current devices also increases in necked traces. A shorter necked region in a trace can conduct its heat into the wider portion. A longer necked trace generates more heat than a shorter necked trace, and heat dissipation into the board and the wider section of the trace occurs at a lower rate. Be mindful of your temperature requirements if you must use necking to route traces to your BGA.
Check With Your Manufacturer
Fanout routing to the BGA requires many vias and buried traces in order to reach all the pins. The major challenge for designers is to implement a fanout strategy that fits the capabilities of your manufacturer. There are several things to keep in mind when devising your fanout strategy, including pad diameter, the number of I/O pins, ball pitch, via types, trace spacing, and the number of layers required to route into the BGA.
Multiple BGAs on a large PCB
Higher density BGAs will require more signal layers. Four to eight layers are for BGAs that support high-density ICs. The pin-density will also constrain the size of your via pads. Maintaining spacing is important in order to prevent crosstalk. If the via pads are placed too close, there is a risk of reduced manufacturing yield due to contact between via pads on neighboring pins.
Altium Designer® uses rules-based design and makes it easy to implement a fanout strategy for high pin-density ICs. The PDN Analyzer™ tool also lets you diagnose signal integrity issues before you move to manufacturing. If you’re interested in finding out more, talk to an Altium expert today.
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