Design For Signal Integrity

March 29, 2019 Jason J. Ellison

When we design PCBs, we start with setting up our Design For Manufacturing (DFM) rules in an EDA tool. However, it is likely that our Signal Integrity rules are the last thing we think about. In this blog, we’ll explore how to incorporate Design For Signal Integrity (DFSI) into our DFM routine.

 

Design For Manufacturing

Before discussing DFSI, let’s first review DFM criteria. The most driving criteria for DFM comes from the PCB’s IPC classification: class 1, 2, or 3. IPC class 1 is for PCBs that just need to work as a whole. There can be cracks or misplaced drills, but if the thing works, then you’re good. These kind of PCBs are found in cheap flashlights, children’s toys, and garage door openers to name a few. IPC class 2 is for electronics that will not just work, but also last a few years being used continuously. These types of PCBs go into higher end electronics like your Playstation or Xbox, electronics systems used for networking, or GPU boards. IPC class 3 is for applications that must work even in harsh environments. These include military applications, medical devices like pacemakers, or PCBs that are destined for space travel.

Once the class is defined, you can move on to the DFM rules. If you want to dig into the IPC document, you can find it at a reasonable price at the online IPC store [1]. If you just want the cliff notes, one of my personal favorite PCB manufacturers, APCT, has a spreadsheet listing the most important features of IPC class 2 and class 3 [2]. However, these requirements are not really useful by themselves. What we really want are the dimensions required to meet the ICP class, and this is where we get into the meat and potatoes of DFM. Since I already mentioned APTC, I’m going to reference them again. They have their PCB DFM requirements posted here [3]. A few examples from the document are minimum copper trace width and spacing, drill holes to copper distance, and how much larger via pads need to be over drill sizes. These are the dimensions to input into your EDA tool, and you’ll get clear error markers when you have problems (Figure 1).

Figure 1. Error marker from a clearance violation (left) and the corrected artwork (right).

So you’ll route your board using these rules and everything should be ok, right? Well maybe, but then again, maybe not. If you are trying to run 10Gb/s of serial data or higher, things could go sideways if you haven’t designed your board with signal integrity in mind. Just like an IPC classification, every high speed communication protocol has an electrical channel standard associated with it. Channels that are 14 Gb/s and below have S-parameter masks that must be met to ensure communication. Channels 25Gb/s and above have S-parameter masks and Channel Operating Margin criteria that need to be met. In terms of how to define your PCB, you can think of these standards as an analogy to the IPC classification. The standard doesn’t give you the means to the end, rather only the requirements you need to achieve. In the same way as the PCB vendors have design criteria to meet IPC standards, we want design criteria to meet the signal integrity criteria. So, let’s get started!

 

Design For Signal Integrity

Connectors

The most obvious limiting factor in a channel is the connector. Fortunately when it comes to high-speed interconnects, the connector companies have done all the work for you. You just go to your favorite connector company’s website, select a data rate and application, and you will be met with solutions that are going to work. The connector companies will even give you the exact geometry to escape from the connector into the board. The hard part is what to do between connectors.

Via stubs

A via stub is formed by the remaining barrel from the internal signal layer to the back of the PCB (Figure 2). The stub creates large energy loss at its resonant frequency with a very low Q. The low Q means it also affects a large band of frequencies around its resonance frequency.

Figure 2. Via stub visualized using Altium  

Signal loss from via stubs is the first problem that occurs after the connector spatially. The connector companies have backdrill recommendations to avoid loss from via stubs. Backdrilling is a process where the remaining via from the signal layer to the side of the board opposite the connector is removed by drilling it away after plating. Up to 10 Gb/s, having via stubs will be ok. However, after 10 Gb/s the loss of signal and added reflections from the stub will cause problems. Thus, after 10 Gb/s backdrilling is recommended.

 

Trace Loss

Ultimately, a link will not work if there is too much channel loss. IEEE standards define loss limits for passive channels of various data rates. 10GBASE-KR is simply limited to 1m lengths (about 13 dB of loss using Megtron 6), 25GBASE-KR is limited to 35 dB at 12.9 GHz, and 50GBASE-KR is limited to 30 dB at 13.28 GHz [4, 5, 6]. Channel loss is driven by skin effect attenuation, surface roughness attenuation, and dielectric attenuation. The relationships are somewhat complex, and are explained well in Advanced Signal Integrity for High Speed Designs [7]. Assuming Megtron-6 PCB material, 7 mil traces with 8 um surface roughness (Rz), the following maximum traces lengths are determined: 1m for 10GBASE-KR, 1.25m for 25GBASE-KR, and 1.21m for 50GBASE-KR. These numbers are before losses from connectors and transitional media. These features within the channel reduce these lengths.

This is only an estimate. To get more consistent results, extract the attenuation coefficient from the board after you’ve created it by using the guidance in [7]. This will include all sources insitu and will yield much better results if you need to re-spin.

 

Differential Traces

For signals up to 5Gb/s, you can probably get away with single-ended traces. Single-ended traces is industry jargon for single traces that carry a serial data stream. Above 10Gb/s, you will need to route everything differentially. Differential traces are a pair of conductors that transmit data where each conduct has data 180 degrees out of phase from the other (Figure 3.). These traces are more immune to noise, and are easier to achieve clean broadband performance in application. However, differential pairs are impacted by skew. Skew is where one half of the pair is electrically longer than the other. Skew is best corrected as soon as possible. However, there will be situations where it is unavoidable. In areas where the signal pair has skew, radiation will be higher. Therefore, keep your traces highly isolated until they are length matched. Once they are length matched, keep the traces apart by at least 5 times the trace width.

Figure 3. A differential pair segment routed in Altium .

We can quantify the effect of skew to determine our absolute maximum length difference in pair. For example, let’s say 1dB of added loss from phase cancelation in Megtron 6 material is when skew is unacceptable. That leads to: 23 mils at 10 Gb/s, and 9 mils at 25 Gb/s and 50 Gb/s (PAM4). Since this is an absolute maximum before a full 1 dB of loss occurs, it is reasonable to divide this number is half for a safety margin.

Another important aspect of traces are their impedance. Impedance is the ratio of instantaneous voltage and current. The traces are easily designed to meet a nominal impedance by using tools such as Polar [9].  However, PCB manufacturers can only guarantee the impedance within a certain percent. Typically, this is 10%. Many board houses offer 7% and 5% tolerances at volume quantities as well. To minimize ISI noise, it is recommended to use 7% tolerance at 25 Gb/s and 5% tolerance at 50Gb/s.

If you have the time and resources, a better way to achieve the target impedance is to build a test board that replicates the board you are designing. Route several traces with varying widths, and do not tell the PCB manufacturer to hold the impedance. This way, you can see what trace dimension achieves your desired impedance using the stackup and PCB manufacturer that you will use in your final application. This technique was most recently demonstrated by Wild River Technology at Design Con 2019 during a panel discussion.

 

Pads

Via pads might be the single most problematic aspect of PCB design for signal integrity. While trace lengths and stubs can be adjusted to avoid loss of signal, via pads are an unavoidable discontinuity. Most PCB manufacturers can meet IPC class 2 by using a via pad, or annular ring (Figure 4), that is 12 mils above the drill size (plus 12 mils for short). A pad of this size causes a very large discontinuity. For data-rates at and below 10Gb/s, plus 12 mil pad is typically acceptable, because the slower rise time filters out much of the noise associated with this via. For data-rates at 25 Gb/s using plus 10 mils instead of 12 mils is wise. For data rates at and above 56Gb/s, use the smallest pad possible, because via discontinuities can cause significant eye closure. The smallest pass possible is typically plus 8mils. Having only 8 additional mils above the signal drill will be difficult for many manufactures to meet IPC class 2. So, be sure to contact your fab house with your requirements well in advance of placing an order.

Figure 4. Annular ring visualized with Altium .

When the annular ring is plus 8 mils, tear dropping is recommended to avoid severing the connection between the trace and via (Figure 5). This can occur with a trace that is the same size or smaller than the drill diameter, and the drill registration is off.  Additionally, teardrops also typically help avoid inductive spikes from the loss of reference around vias as well.

Figure 5. An annular ring with 10 mil drill, 18 mil (plus 8 mil) annular ring, and a 10 mil trace.

 

Summary Table

A table can be made for any material. In table 1, Megtron 6 with 7 mil wide traces and 4 um

of surface roughness is considered. This is a nice starting point for your DFSI. If you have your own DFSI criteria, feel free to leave it in the comments and help the community!!

 

Table 1. DFSI Rules

 

10GBASE-KR

25GBASE-KR

50GBASE-KR

Data Rate

10.3125 Gb/s

25.78125 Gb/s

51.5625 Gb/s

Back Drilling

Not Required

Required

Required

Maximum Trace Length (m)

1

1.25

1.21

Maximum Differential Skew (mils)

11.5

4.5

4.5

Impedance Tolerance

10%

7%

5%

Signal Via Annular Ring

Drill +12 mils

Drill + 10 mils

Drill + 8 mils

 

 

References:

[1] IPC-A-610 Qualification and Performance Specification for Rigid Printed Boards, Feb, April 2010.

[2] APCT IPC-6012D/DS Requirement Differences Per Product Class, web: https://www.apctinc.com/wp-content/uploads/2018/04/APCT_Wallingford--IPC-6012D-Requirement-Oct2017.pdf

[3] APCT Corporate Manufacturing Capabilities, web: https://www.apctinc.com/capabilities/

[4] IEEE 802.3ap Ethernet Operation over Electrical Backplanes, May 2007

[5] IEEE 802.3bj Physical Layer Specifications and Management Parameters for 100 Gb/s Operation Over Backplanes and Copper Cables, June 2014

[6] IEEE 802.3cd Media Access Control Parameters for 50 Gb/s and Physical Layers and
Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operation, December 2018

[7] Janezic, M.D., J.A. Jargon, “Complex Permittivity Determination from Propagation Constant Measurements,” IEEE Microwave and Guided Letters, vol. 9, no. 2, (1999), pp. 76-78

[8] S. Hall, H. Heck, Advanced Signal Integrity for High Speed Digital Designs, Wiley 2011

[9] Polar Instruments, web: https://www.polarinstruments.com/

 

About the Author

Jason J. Ellison


Jason J Ellison received his Masters of Science in Electrical Engineering from Penn State University in December 2017.

He is employed as a signal integrity engineer and develops high-speed interconnects, lab automation technology, and calibration technology. His interests are signal integrity, power integrity and embedded system design. He also writes technical publications for journals such as “The Signal Integrity Journal”.

Mr. Ellison is an active IEEE member and a DesignCon technical program committee member.

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