Everything You Need for Successful PCB Stackup Design

January 16, 2019 Lee Ritchey

There are three demands placed on stackup design: controlled impedance, crosstalk control and the need for interplane capacitance. Some fabricators could get the impedance right in a stackup, but there is no way for them to account for the other two. This responsibility rests with the design engineer who is the only one who knows what is needed and how to implement the needed control.

This information is intended to provide guidance on the process of designing PCB stackups. It is useful to look at the evolution of technology as time has passed in order to see how the demands on the PCB stackup have changed.

In the early days of PCB fabrication, logic circuits were so slow that the only concerns were how to make connections between logic or discrete parts and provide a path for the DC power to each part. All a needed to do was provide enough signal layers for all of the wires and enough copper in the power paths to deliver the DC power with a minimum of sag or droop. It did not matter what the glass cloth used in the laminate and prepreg was or what the resin system was or how thick each piece of laminate was. The goal was the lowest priced PCB that would stand up to the soldering process.

Eventually, ICs became fast enough that problems such as reflections and cross talk mattered. The logic family that did this was ECL. At that time, the primary users of ECL were large computer companies such as IBM and Cray Research. These companies had engineers on staff who did the impedance calculations needed to design stackups and had their own in-house PCB fabrication facilities as the public market fabricators did not yet have the capabilities to exercise control of fabrication necessary to meet their requirements.

Altium Designer® 's Stackup Materials ensures your boards are always built with only compliant materials.

In the mid-1980s TTL, the most common logic type then in use, became fast enough that reflections became a problem requiring PCBs to have controlled impedance. Few, if any, of the engineers designing with TTL and CMOS, had any understanding of how to achieve a controlled impedance PCB, so they would demand that the fabricator deliver PCBs with a known impedance, usually 50 ohms. Fabricators did not have this capability as their skill set included plating, etching lamination, and drilling. Still, engineers demanded that the fabricators do the impedance calculations. The author was around during this time and spent many hours helping fabricators develop the ability to calculate impedance. Their skill at this task was very hit and miss and, in many cases, still is today.

By the mid-1990s, speeds had increased to such an extent that most products were failing EMI due to the need for capacitance that worked above 100 Mhz. None of the discrete capacitors placed on the power rails could solve this problem due to their mounting inductance. This gave rise to what is known as interplane capacitance or buried capacitance. Interplane capacitance is created by placing the power and ground planes very close to each other, typically, less than 3 mils.

So, now we have three demands placed on stackup design: controlled impedance, crosstalk control and the need for interplane capacitance. Some fabricators could get the impedance right in a stackup, but there is no way for them to account for the other two. This responsibility rests with the design engineer who is the only one who knows what is needed and how to implement the needed control.

By the mid-2000s, speeds of many differential pairs got so fast that the glass weave used in the laminate and prepreg could induce a phenomenon known as skew that destroyed the signal. Skew is the misalignment of the two sides of a differential pair as they arrive at the receiver. In addition, losses in the laminate began to affect these high-speed signals, forcing the engineering team to seek low loss laminates that satisfied loss goals as well as all of the above requirements.

In Altium 19 you can manage multiple impedance profiles for stripline, microstip, single or differential pairs. 

For all of the reasons discussed above, the design engineer must take charge of design. To do this successfully a thorough understanding of the fabrication process and materials is essential. This section will cover all the topics involved in designing of PCB stackups that meet the four constraints: controlled impedance, managing cross talk, creating adequate interplane capacitance and specifying the correct weave to manage skew.



In order to make the best decisions when designing a PCB stackup, it is useful to understand how multilayer PCBs are manufactured. There are a number of methods used to fabricate multilayer PCBs. The most common and most economical is called foil lamination. Figure 3.1 is a pictorial of a typical six-layer PCB. Notice that there are three basic components in the stackup. These are: sheets of copper foil in the top and bottom of the stackup, sheets of prepreg and sheets of laminate.

The outer layers are always solid sheets of copper foil until after the stackup has been laminated and drilled.  The reason for this is to provide a path for the plating current used to plate copper in the drilled holes used as vias and component leads. The material known as prepreg or B stage is woven fiberglass cloth that has been coated with the resin system chosen for a particular design. This resin has been only partially cured and will serve as the “glue” when the stackup goes through lamination. The component laminate is the same glass/resin material as the prepreg. It has a layer of copper in each side that is bonded to the glass/laminate in a press that cures the resin, resulting in a rigid piece of material called laminate. The inner signal and plane layers will be etched on these pieces of laminate, two at a time.


Figure 3.1 A Six Layer PCB Stackup Using foil Lamination

Notice that the layers are created in pairs.  For optimal manufacturability, stackups should always be designed with even multiples of layers.

An alternate method for laminating a multilayer PCB is known as “CAP” lamination.  Figure 3.2 is an illustration of a six-layer PCB created using cap lamination.  Notice that there are three laminate components and only two prepreg layers and no foil layers.  This is the original method used to create multilayer PCBs. It is more expensive than foil lamination due to the need to manufacture three laminate pieces.  It is only used when a rigid material such as Rogers 4350 must be placed between layers 1 and 2.

There are other forms of lamination such as build up lamination which involve multiple lamination cycles and blind and buried vias.  These will always be more expensive than either foil or cap lamination due to the extra process steps required and will be discussed at the end of this chapter.

Figure 3.2 A Six Layer PCB Stackup Using CAP Lamination



Figure 3.3 is a diagram illustrating the major steps involved in the manufacture of a multilayer PCB. A major consideration in this process is achieving tight control over the impedance of the transmission lines. There are three places in this process that are the main sources of impedance variation. These are: plating and etching the traces on the outer layers, etching the signal inner layers and the lamination cycle.

Etching affects the impedance through the process of removing the unwanted copper on the outer layers between the traces. This involves placing an etch resist on all the copper areas on the outer layers that will remain after etching. As the etching solution etches down through the copper layer it also etches sideways resulting in traces with the width at the top narrower than at the bottom, creating a trapezoid. This trapezoidal shape results in an impedance higher than is expected by the impedance predicting tools which often assume that the trace shape is a rectangle. When the starting copper thickness is made larger, the potential error grows larger. Therefore, the thinner the starting copper thickness, the more accurately the impedance can be controlled. The thinnest copper foil that can be handled without special fixturing is ½ ounce copper which is, on average, 0.6 mils or 15 microns. For signal integrity considerations, any trace layer at least 2 microns thick is more than enough copper to satisfy loss rules. Therefore, it is advisable to use copper foils for signal layers no thicker than ½ ounce.

In the case of outer layer trace formation, the traces are first plated up with copper as the plating is deposited in the holes. Then, the unwanted copper is etched away to form the signal traces. Unless great care is exercised by the fabricator, the outer layer trace tolerances will be far more than the +/-10% tolerance that can be achieved on inner layers. For this reason, it is advisable to use only inner layers for signals that require tight control over impedance.

During the lamination cycle, the resin in the prepreg layers melts and flows into the voids in the adjacent copper layers. In addition, the pressure used to achieve lamination throughout all the layers squeezes some of the prepreg resin out the edged of the PCB, resulting in a thinning of the prepreg layers.

Figure 3.3 Multilayer PCB Manufacturing Process Flow

The most important dimension in controlling impedance accuracy is the distance between the trace layer and the nearest plane. If this is prepreg, the impedance will vary substantially. Therefore, it is advisable to always mate signal layers with plane layers across a piece of laminate. This is the main reason that RF engineers use CAP lamination. It puts laminate between layer one and layer 2 so the RF traces on layer one are formed as accurately as possible.


Er or DK   

When discussing laminate systems, the term Er or DK is used. This term is relative dielectric constant. It is referring to the effect that a dielectric has on the parasitic capacitance of a structure as compared to that same structure in a vacuum. In transmission lines, the parasitic capacitance between the trace and the plane layer is a major factor in determining the impedance of a transmission line.

Figure 3.4 is a schematic diagram of a transmission line. Notice that the parasitic capacitance is between the transmission line and the plane layer over which the transmission line is routed.

Figure 3.4 Schematic Diagram of a Transmission Line

Equation 3.5 is used to calculate the impedance of a surface or microstrip transmission line. Notice that er is in the denominator. Increasing er results in a lowering of the impedance. Lowering er results in an increase in the impedance. This is due to the fact that a higher er  causes an increase in the parasitic capacitance. Equation 3.6 can be used to calculate impedance if LO and CO  are known.

As can be seen, an increase in CO  results in a lowering of the impedance.

Equation 3.5 Impedance Equation for Surface Microstrip Transmission Line

Equation 3.6 Impedance Equation and Calculation Using Lo and Co



The previous discussion made it clear that accurate knowledge of the available laminates is essential.  There are dozens of possible laminates to choose from sourced in North America, Asia, and Europe. For optimal manufacturing, it is advisable to select a laminate system that is readily available in the region where the PCBs will be fabricated. A problem often arises when companies prototype their designs on one continent and manufacture in volume on another. This necessitates selecting a laminate system available in both places. As the fabrication operations have matured in Asia, there is more and more laminate available on a global basis, so this problem has eased.

A significant problem occurs as an engineer seeks laminate data. The classic data sheet used in the industry is a two-page document whose content is defined by an IPC standard. Unfortunately, this document only has typical electrical information such as typical er and typical loss tangent, often measured at 1 MHz. Both of these quantities vary with both frequency and the ratio of glass to resin in each thickness of laminate and prepreg. Figure 3.5 shows how the DK or er of some sample laminate systems changes with both frequency and resin content. The thin lines are laminates that contain about 43% resin which is the resin content of ultra low-cost laminates like those used in toys or where laminates are thick. In high layer count PCBs, the resin content is above 50% to allow enough resin to fill the voids in adjacent signal and plane layers during lamination. The thick black line is a resin system such as epoxy with 55% resin.

Figure 3.5 Relative Dielectric Constant vs. Frequency Chart


A question that arises is at what frequency should impedance calculations be done? As it turns out, modern ICs have rise times well below 1 nanosecond. It is the rise time that is important when managing reflections. The first harmonic of a 1 nanosecond edge is about 2 GHz. Therefore, to have an impedance that is properly matched at this frequency the DK used in this calculation should be the 2 GHz value. Since the DK is essentially flat above 2 GHz, this value will work at all faster rise times.

One of the reasons that PCB fabricators do not get impedance calculations right is that they often use the typical value of DK listed on the data sheet which is usually the 1 MHz value. If the DK varies with both frequency and resin content where does one obtain the correct values? Table 3.1 is a list of several thicknesses of laminate for a resin system manufactured by Isola called FR408HR. This type of information is available from every major laminate manufacturer and is contained in the materials libraries of most of the impedance calculating tools such as Polar Instrument’s SI8000. If a fabricator is relied on to perform impedance calculations, it is imperative that they be in possession of this information along with the classic two-page data sheet

Figure 3.6  DK vs. Frequency DK Table example

Table 3.1 DK Table for Isola FR408HR Laminate, Table courtesy of Isola Laminates

Table 3.1 lists several thicknesses of laminate starting at 2 mils (50 microns) up to 6 mils or 150 microns. Included are the type of glass cloth used and the resin content. Also, notice that the DK measurement frequencies start at 100 MHz rather than the 1 MHz that is often used by fabricators to calculate impedance and that the DK is relatively constant above that frequency. This is the starting information an engineer needs in order to design PCB stackups and arrive at accurate impedance calculations.



Historically, the industry has used equations to calculate impedance. Equation 3.5 is one such equation. All of the equations that have been used for the three types of transmission lines, surface microstrip, buried microstrip and stripline, were developed by building a large number of test PCBs, measuring their impedances, sectioning the PCB to measure the dimensions, and then doing curve fitting to arrive at an equation that approximates the measured numbers. These equations are moderately accurate when used with dimensions near those used in the development process. Unfortunately, the dimensions in most PCBs currently being designed are not in that range. As a result, substantial errors can and usually do result.

Figure 3.7 is a plot comparing the impedance prediction of the three most common impedance equations to what a field solver using Maxwell’s equations predict. The dimensions held constant are: trace height- 5 mils, trace thickness- 1.4 mils, dielectric constant 4. The curves with squares are what the equations predict. The curves with the diamonds are what the field solvers predict. Many tests have been done to determine the accuracy of field solvers with very good correlation of predicted impedance to that which results from fabricating a PCB to the field solver dimensions. The author has built dozens of PCBs using field solver predictions with excellent agreement, so they are a good reference against which to compare the equations.

As can be seen, the two microstrip equations (purple and red) vary substantially from the field solver results. Since field solvers are integral parts of all SI tools, they should be used instead of equations when calculating impedance.

Figure 3.7 Comparison of Field Solver to Equation Impedance Predictions



Once the number of power planes, ground planes, and signal layers have been determined for a given design arranging them in such a way that signal integrity rules are complied with and power delivery needs are met is a series of tradeoffs. If there is a need for interplane capacitance it will be necessary to arrange the layers so ground and voltage planes are spaced close to each other. Figure 3.8 is an example of making tradeoffs between routing layers and power plane capacitance for a ten-layer PCB. The stackup on the left side of Figure 3.8 has six signal layers, but only has one pair of planes closely spaced. This is good for routing space, but not so good for power delivery if there is a need for interplane capacitance. The stackup on the right has only six routing layers, but it now has two sets of plane pairs. This is good for interplane capacitance, but not as good for routing space.

Figure 3.8 Two Examples for Ten Layer PCB

In both cases above, all the signal layers are mated with planes across pieces of laminate except the two outer layers. If the outer layers are to be used for controlled impedance traces, allowance must be made for the fact that their tolerance will not be as good as the buried signal layers.

Once the arrangement of layers has been determined, the next step is to select the thickness of each dielectric layer to achieve the best performance at the lowest cost. To minimize crosstalk, it is advisable to select the thinnest laminate that meets SI goals for the space between signal layers and their plane partners. Once this is done, the trace width needed to achieve the target impedance is calculated. Following this, the thickness of the prepreg between the power planes is selected to satisfy the breakdown voltage requirements and allow enough resin to fill the voids in the adjacent planes. This will usually be a single glass ply that begins three mils thick and presses down to about 2.5 mils.

In the example on the right in Figure 3.8, there are three prepreg layers that remain to be chosen. These are the one in the center of the stackup and the two just below the outer layers. (The outer layers in this stackup are not usable as controlled impedance layers, so their height above their underlying planes is not critical.) The thickness of all three of these spaces can be used to add material in order to arrive at the final thickness desired as changes in thickness in these three areas have little effect on the overall performance of the PCB.



As the speeds of signals continue to increase, the demands placed on the PCB become more complex. Some of those demands, as mentioned above and later in the differential signaling and power delivery chapters of this manual, are controlled impedance, controlled crosstalk, interplane capacitance, and glass weave style control.

For these reasons, the documentation required has become more complex as well. The stackup drawing must contain more information than in the past and the fabrication notes will need to be expanded. Figure 3.9 is an example of the amount of information that must be included in the stackup drawing to insure the PCB is correctly fabricated. Notice that there is no impedance information on the stackup drawing. The reason for this is that all the other requirements must also be met as well. Therefore, the stackup drawing specifies the overall cross section of the PCB that meets all the SI goals. The design engineer must determine all of these including impedance and specify the total cross section.

Figure 3.9 Stackup Drawing Example

Fabrication notes must contain more information than has typically been necessary with slower designs. Table 3.3 is a representative example of fabrication notes needed for a design that is not fast enough to require control of glass weave style and overall path loss.

Typical Fabrication Notes for High Performance PCBs:

  • Reference General Specification for Printed Circuit Boards #XXXXXXX
  • Any deviation from these instructions must be approved in writing by principal or agent.
  • Material: Use only materials specified in stackup drawing accompanying design.
  • Board Lamination: Overall thickness: 0.xxxx” ± the lesser of 0.010” or 10%.
  • Copper weight: see layer stackup drawing.
  • Drilling: All holes to be located by X & Y coordinates from NC drill data supplied. See separate Drill Table for drilled hole sizes and quantity. Pad stacks are designed for the drilled hole sizes shown. Drill Table will contain special callouts for Press-Fit holes. Do not change drill sizes.
  • Minimum annular ring of 2 mils, unless otherwise specified. Also see note 20.
  • Copper plating: Hole wall copper plating to be 0.001” minimum (drill size - 0.002").
  • All exposed copper to be plated with electroplated gold over electroplated nickel. 5-15 micro-inches gold over 150 micro-inches nickel minimum. (Palladium allowed between nickel and gold). Immersion silver may be allowed in special cases.
  • Soldermask: Liquid photo-imageable solder mask to be applied over bare copper or gold/nickel plating unless otherwise specified. Color- green.
  • Legend/Silkscreen: Use nonconductive white ink.
  • Mark with supplier ID and date code on bottom or far side.
  • All inside corners and slots shall have 0.062 radius ±0.005” or less radius.
  • No modification of film without prior authorization. For exceptions see notes 16 & 20.
  • Stripes of copper may be plotted on each layer on one side of the PCB edge as shown on fabrication drawing. These “stacking stripes” are intended to be exposed when the PCB is removed from the panel. Do not remove/modify stacking stripes.
  • Compare CAD net list to net list generated from Gerber data prior to fabricating board. Resolve differences prior to building board.
  • Non-functional pads are to be removed from all inner layers.
  • Conductors: Width and Spacing: Build to Gerber data, however, compare widths to Fabrication Drawing Data Set Table and resolve differences prior to fabricating board.  GERBER TRACE WIDTHS ARE FINISHED TRACE WIDTHS. Finish width accuracy on inner layers ±0.0005”. Finished width accuracy on outer layers ±0.001”. Fabricator may add manufacturing allowances to trace widths in working film only to accomplish the specified finished trace width.
  • This is a controlled cross-section PCB. All fabrication instructions must be complied with in order to assure valid results on completed assemblies. Etch all trace to widths specified in Gerber files. All dielectric thicknesses specified on layer stack-up cross-section on Fabrication drawing.
  • First delivery to include a copy of the stackup sheet used to select laminates and a 500X view of the stacking stripes with dimensions of all laminate layers.
  • Teardrop only on 23 mil and smaller through-hole pads at trace exit location. For 23 mil pads, flash another 23 mil pad off set from pad center by 3 mils.
  • Thieving allowed on outer layers to insure uniform plating. Thieving shall be no closer than 0.100” from any other copper feature on the outer layers and shall not be within 0.100” of traces on the first buried signal layer beneath the outer layers. Thieving pattern shall be at the supplier’s discretion and not be solid copper.
  • Dimensions of dielectric layers and copper thicknesses and width of 5 mil traces protruding from PCB to be measured on one PCB of each lot using stacking stripes at 500X magnification. Report to be included with first delivery along with copy of traveler used to fabricate PCB showing laminates used in fabrication.
  • Drilled hole true position difference from CAD data is not to exceed 0.005” TIR.
  • Via capping is required on 12 mil vias from BGA side with epoxy followed by LPI Soldermask. Opposite side Soldermask encroachment onto via pads to be 0.008” over drill diameter.



There are a number of places in the fabrication process where things can go wrong. Examples of problems are: traces are the wrong impedance; the layers are not in the correct order; dielectrics are the incorrect thickness; and the glass weave style is incorrect. Without some nondestructive way to determine a PCB has been built correctly problems like this will only be discovered after assembly, which is too late. Some form of test structures need to be added to allow checking at receiving inspection. The author has learned that two are needed. These are: impedance test traces on every signal layer and stacking stripes plotted along one edge of the PCB that are visible when the PCB is cut from the fabrication panel. Figure 3.10 illustrates these structures.

Referring to notes 14 and 22 of the fabrication notes in Table 3.3 instructions have been provided on how to handle these test structures.

Figure 3.10 Test Structures Example

Some may think that adding these stacking stripes is an extra step that is not necessary. Figure 3.11 is a view of the stacking stripes for a 2- layer PCB with the layers in the wrong order. Layer 22 is where layer 11 should be and layer 11 is where layer 22 should be. If this error had not be caught at receiving inspection by a sharp-eyed person, thousands of dollars of parts would have been assembled onto this PCB and it would not have worked properly without anyone being able to determine what was wrong.

Figure 3.11 What Not To Do



Build up is a method of fabricating a PCB by adding layers using multiple steps of the lamination process. The reason for doing this is to allow the use of components on both sides of a PCB with such high density that it is not possible to drill component lead holes all the way through the PCB without hitting the mounting pads on the opposite side. Many of the connections are made using blind and/or buried vias. Figure 3.12 illustrates the various kinds of blind and buried vias that can be used in a build-up PCB. The most common build-up PCB is found in a cell phone. A core PCB of six layers is fabricated using the standard foil lamination process described earlier. A piece of prepreg is added to each side of the core along with sheets of foil and the combination is laminated. Blind vias are drilled from the two outer layers to the next layer down creating blind vias. This process may be repeated a number of times to allow connections to be made to all of the signal and power pins of each component resulting in a “built-up” PCB.

Some clarification is in order about what constitutes a blind via and a microvia. The term microvia is often used to describe a blind via. They are not necessarily the same thing. By IPC definition, a microvia is any drilled hole 8 mils (200 microns) in diameter. It may be a through hole via or a blind via. A blind via is a via or hole that begins on one side of a PCB but does not go all the way through no matter its diameter. A buried via is one that is inside a PCB and does not exit either side.



The final cost of any PCB depends on several factors. Among these are the number of layers, the plating requirements and the total number of operations performed to create all the holes. It should be clear that for a given number of layers, adding blind vias will increase the cost as will employing build up technology. Table 3.4 illustrates how the cost of a PCB goes up as layers are added and second operations such as blind vias and multiple lamination steps are added. This table was compiled by a number of fabricators involved in all of the types of operations shown. Clearly, adding extra steps such as build up and blind vias increases costs rapidly.

Table 3.4 PCB Cost vs. Layer Count, Table courtesy of Nechan Naicker and NCAB Group



The subject of thieving often arises when discussing PCB fabrication and is often accompanied by confusion as to what it is, when it is used, who adds the thieving and where it is added. Note 21 in Table 3.3 allows a fabricator to add thieving and where it can be added.

Figure 3.12 is an example of thieving added by a fabricator. Notice that there are small dots of copper and are not connected to any circuits on the PCB. These dots are added by the fabricator prior to plating the copper in the holes and on the pads to provide a more uniform distribution of copper. This is done to insure the plating current is uniform across the entire surface so that all features receive the same amount of copper. The primary consideration is the holes into which press fit connectors will be inserted. The tolerance on these holes is usually very tight.

Figure 3.12 Typical Thieving



Flooding the unused space in signal layers is a practice that was used in the early years of multilayer PCB lamination. Fabricators would often stack several PCBs in a press opening without anything separating them but thin sheets of cardboard. During the press cycle, areas with little copper such as the open spaces in signal layers would press out thinner than the rest of the PCB. This resulted in an uneven surface that could make soldering of high pin count BGAs difficult. At that time, the solution was to add copper in the signal layers to “copper balance” the PCB. This copper was often connected to ground and called ground flooding.

With the advent of controlled impedance PCBs with two signal layers between a pair of planes, this practice could not be used as it altered the impedance of traces in adjacent layers to the fill copper. The flatness problem was solved by inserting thin sheets of stainless steel between each PCB stackup or by inserting only one stackup in each press opening. Ground flooding is no longer needed.

Altium is a PCB design tool that experts recommend for PCB stackup design. Click on the free trial to try it for yourself or watch the OnTrack Podcast episode with guest Lee Ritchey below.


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About the Author

Lee Ritchey

Lee Ritchey is considered to be one of the industry’s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge, an engineering consulting and training company. He conducts on-site private training courses for high technology companies and also teaches courses through Speeding Edge and its partner companies.

In addition, Lee provides consulting services to top manufacturers of many different types of technology products including Internet, server, video display and camera tracking/scanning products. He is currently involved in characterizing materials for ultra high speed data links used throughout the Internet.

Prior to founding Speeding Edge, Ritchey held a number of hardware engineering management positions including Program Manager for 3Com Corporation in Santa Clara and Engineering Manager for Maxtor. Previously, he was co-founder and vice president of engineering and marketing for Shared Resources, a design services company specializing in the design of high-end supercomputer, workstation and imaging products. Earlier in his career, he designed RF and microwave components for the NASA Apollo space program and other space platforms.

Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 2004, Ritchey contributed a column, “PCB Perspectives” which appeared on a monthly basis in the industry-renowned trade publication, EE Times.

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