Meeting Standards: IPC 6012 Class 3 Annular Ring

February 7, 2019 Altium Designer

 Annular rings as via pads on a blue PCB

 

If you’re like me, things like embedded computing and device miniaturization are fascinating topics. Moore’s Law is causing IC manufacturers to build successively smaller devices, and PCB design standards will eventually have to follow suit.

 

Working under industry standards may seem onerous at first glance, and working under certain standards may seem to eliminate some design freedom. In reality, industry standards are designed to ensure that certain products meet critical specifications. They also ensure that your device will be compatible with other devices designed under the same standards. Keeping these standards in mind during design will help ensure that your design is reliable in the long run.

IPC Standards for Annular Rings

The IPC standards define three product classifications (Class 1, Class 2 and Class 3) based on the required level of device reliability. Each of these classes defines guidelines for fabrication, cleaning, and inspection of PCBs for different applications. Issues such as component placement, via hole plating, residual contaminants, trace sizes, and other design aspects are all addressed in the standards for each of these classes.

 

Devices that meet class three requirements require continuous uptime with high performance. Devices meeting this class should be designed for use in harsh environments and the devices must function when required. Class 3 products are often found in a number of important applications, including in the medical and aerospace fields.

 

Specification on annular rings are designed to assure a large connection area between a via pad, the drill hole, and any component that may be mounted on it. When designing a multi-layer PCB with the goal of complying with IPC 6012, the important dimension is pad diameter. Meeting the minimum IPC Class 3 annular ring requirements requires that the pad size be large enough to accommodate the diameter of the via.

Internal vs. External Annular Rings

Designing reliable in-pad vias also requires that designers make decisions regarding annular rings on the interior and exterior layers of a PCB. Annular rings on the interior layers are called non-functional pads, and designers should consider removing them under certain conditions. On the exterior layers, annular rings will determine which type of via structure (laser microvia or drilled-and-filled) to use in a multilayer PCB.

 

The annular ring diameter must be at least 50 microns for pads on the external board layers for plated through-hole vias according to Class 3 standards. For non-functional pads on plated through-hole vias, the annular ring diameter must be at least 25 microns. Unsupported via pads must be at least 150 microns, and via pads should be located at least 0.006” away from adjacent copper features.

 

The end goal of Class 3 annular ring size specifications is to minimize the chances of mechanical failure during operation. These standards are very important for ensuring the reliability of SMT components and fine-pitch BGAs mounted on your PCB.

 

Multiple BGAs on a green PCB

No matter how you fanout a large BGA know that Altium Designer has your back

 

 

Newer CPUs and other components use BGA packages with less than 1 mm small ball pitch, and ball pitch is only expected to decrease in the future. These BGA packages require design and manufacturing processes that are not currently addressed by the Class 3 standards. In these fine pitch BGA packages, the Class 3 pad size requirements can result in unroutable signals.

 

Signal traces routing to and from these fine pitch BGAs will pass too close to nearby pads. Reducing the trace width can reduce the power delivered to the component mounted on the BGA. One solution is to use teardrop-shaped pads instead of circular pads. These teardrop pads ensure reliability required under Class 3, while still providing the spacing required between pads and traces.

Designing for Manufacturing with Class 3

The ideal hole placement in a pad is dead center according to Class 3 specifications. However, off-center hole placement is also acceptable. Placing the hole close to the trace connection does not meet Class 3 requirements as this weakens the connection between the trace and the pad. Placing the hole so that it touches the edge of the pad is also unacceptable under Class 3 specifications. The via hole must be no closer that 0.05 mm from the edge of the via pad.

 

Manufacturing tolerances should be able to meet these hole placement requirements for devices that are designed according to Class 3 specifications. The size of annular rings used in via pads must be enlarged compared to other specifications in order to meet the drill hole requirements of the Class 3 specifications.

 

CNC soldering machine for PCB manufacturing

Ensure your design software can keep up with your via demands

 

 

There are a number of other specifications on vias defined under the IPC 6012 Class 3 specifications. These specifications include requirements on board thickness, copper plating in various via structures, and the presence of any copper voids in filled vias. A PCB design software package with the best CAD tools can ensure that your device meets many of these requirements. Working with the right manufacturer can help you meet the other requirements.

 

If you need to ensure that your next multi-layer PCB meets appropriate design standards and the tolerances of your manufacturer, Altium Designer 18.1 has top-notch CAD and via design tools. You can place and design via-in-pad structures with extreme accuracy and rest assured that your design will meet industry standards. To find out if Altium Designer is right for you, download your free trial. Talk to an Altium expert today if you want to learn more.

 
 

About the Author

Altium Designer

PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

Visit Website More Content by Altium Designer
Previous Article
Altium at IPC Apex Expo Week in Review
Altium at IPC Apex Expo Week in Review

Find out what happened this week at IPC Apex Expo and more on the Altium PCB design blog and Youtube Channel.

Next Article
 Choosing Equivalent ICs in Your PCB
Choosing Equivalent ICs in Your PCB

Learn more about choosing equivalent ICs in your PCB in this article.

×

Enjoying our blogs? Subscribe to our mailing list to have a weekly Altium blog digest sent to your inbox.

First Name
Last Name
Country
Acknowledging Altium’s Privacy Policy, I consent that Altium processes my Personal Data to send me communications, including for marketing purposes, via email and to contact me by phone.
!
Thank you!
Error - something went wrong!