Pad Stack Design And Fine Pitch Components, Part 2

December 5, 2019 Kella Knack

What happens when you try to route two traces between pins on 1mm and below pitch BGAs? In Part 1 of this article, I reviewed the various aspects of unplated holes in the pad stack and what is needed to calculate the complete dimensioning of the finished hole size of the plated through-hole. Within this article, an analysis was done to determine how much room there was for traces between BGAs with a pin spacing of 1 mm on high layer count PCBs.

In this, the second part of our exploration of pad stack design and fine pitch components, we will address what happens when the lead pitch is reduced to 0.8 mm or below, the manufacturing tolerances for components with these pitches, and how conventional routing will not suffice in these scenarios.

What’s Different, What Remains the Same?

As noted previously, there are a number of proponents who advocate routing two traces between the pins of 1 mm pitch BGAs. (This is often recommended as a way to have lower layer count boards that cost less). Even if the most optimistic dimensions are used that still result in trace widths and trace spaces that process properly in a volume PCB shop, the traces and spaces will be at least 4 mils each. This means that the web will need to be 12 mils wide. Note: there are a few fabricators that will do 3 mil lines and 3 mil spaces but they are not common and it is wise to design for volume shops if a product is to be manufactured in volume. In this scenario, the clearance pad or opening in the power plane can be no larger than 25.37 mils or 0.644 mm. There still has to be room for plating, drill size, drill wander and insulation. To meet these goals, one of the foregoing dimensions will have to be compromised. This will most likely result in holes that are so small that the plating is unreliable. Or, the insulation dimensions will be so small that in worst case conditions, there will be shorts between the plating in the hole and the planes or traces due to chemical wicking up the glass fibers (this was described in Part 1 of this article).

So what happens when a 0.8 mm pitch BGA is used? The first factors that need to be addressed are the manufacturing tolerances. With a 0.8 mm pitch BGA, the lead pitch is 31.5 mils.  And, the clearance holes in the plane would need to be 32 mils for a 12-mil drilled hole. This would result in no web at all in the planes and certainly no room for signal traces in signal layers.So, if 0.8 mm parts must be included on a high layer count PCB (as will be the case with many DDR2 memory components which have 0.8 mm pitch balls) how can they be connected up and still result in a reliable, manufacturable PCB?

Figure 1 depicts one approach to this problem. In this instance, the pads of the 0.8 mm pitch component have been fanned out to an array of pads or holes on a 50-mil pitch. This matches the 50-mil pitch of the high pin count BGAs on the PCB. The smaller round pads are the 0.8 mm pitch pads for the BGA and the larger round pads are for the vias on the 50-mil pitch hole array. Note: This method works just as well for 1 mm pitch components. It is how the memory ICs were fanned out on the main PCB found within the original Microsoft 360 Xbox

Traces of a 0.8 mm ball grid array (BGA) fanned out to a 50 mil pitch hole array

Figure 1. A 0.8 mm BGA Fanned out to a 50 mil Pitch Hole Array

By redistributing the pins of the 0.8 mm part to a 50-mil pitch array of holes, the requirements of the BGA and the PCB have both been met. When the pin count grows high, as is the case with some Texas Instruments components, this technique will not work as there are too many pins to fan out to the 1 mm pitch. When this happens, it is necessary to resort to laser-drilled blind vias and/or build up methods with buried vias to successfully connect all of the pins. The downside to this approach is that the resulting PCBs become more difficult to manufacture and can also be quite expensive.

Initially, it was not clear as to why TI and other IC manufacturers chose to house their components in such small packages when there was so much real estate available on the surface of almost any PCB. Now, the ever-increasing feature and functionality demands of current and future electronic products necessitate that small form factor components has become the rule and not the exception. This is especially true when you consider just how many features and performance capabilities there are in today’s real-estate limited products such as mobile phones and other hand-held devices. So, what happens when we scale down to even smaller geometries such as 0.5mm pitch memory components?

Figure 2 illustrates one way to solve the problem. In this solution, the component leads that must connect to internal power layers are fanned out to 1 mm pitch and have through-hole vias. All of the other pins (signal pins) are either connected on the outside layer or are connected to traces on layer 2 using a laser-drilled blind via.

Photograph of the top layer of a PCB showing the footprint of a 0.5 mm pitch memory ball grid array (BGA) fanned out using a combination of through and blind vias.

Figure 2. A 0.5 mm Pitch Memory BGA Connected Using a Combination of Through and Blind Vias

The curious thing about this package is that when the fan-out was done to allow connecting all of the pins to inner layers, it required as much board real estate as it would have if it had been packaged in a 1 mm pitch BGA. If this had been done, there would not have been a need for the laser-drilled blind vias, the PCB would have cost less, and it would have had the same functionality. 

Summary 

Pad stack design covers a number of features in a PCB hole including whether the hole is plated or unplated and whether it is through-hole, blind or buried. The pad stack components include the drilled hole size, the finished hole size, the size of the pads plotted on the outer layers, the pads plotted on the inner layers, the clearances in the planes through which the holes pass, and the clearances of the solder mask that is applied to the outer layers of the PCB. With the advent of 1 mm and below fine pitch components, there is a risk in fabricating to these dimensions relative to the challenges associated with manufacturability, performance reliability, and overall cost. 

Continue reading about planning your multilayer PCB stackup in Altium Designer® or talk to an Altium expert today to learn more.

References: 

  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 

  2. Ritchey, Lee W., “What Happens When 0.8mm and Smaller Components are Placed on High Layer Count PCBs?” Current Source Newsletter, Issue 7, October 2007

About the Author

Kella Knack

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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