PCIE Layout and Routing Guidelines

April 10, 2019 Zachariah Peterson

Motherboard with PCIe slots on a blue background

Opening up a computer as a kid and staring at the complicated mess of card slots, chips, and other electronics on a motherboard always made me wonder how anyone could keep it all straight. Learning more about PCB design for computer architecture and peripherals made me appreciate the dedication PCB designers have for building great electronic devices.

Modern GPU, USB, audio, and networking cards all run on the back of the same computer peripheral architecture: PCI Express. If you’re new to PCB design for PCIe devices, information on the topic is fragmented, with some information held as closely guarded corporate secrets. Fortunately, the basic specifications can be broken down into actionable design rules. You can easily layout and route your next PCIe device using the right PCB design software.

 

Trace Routing Specifications

Compared to most high speed devices, the three PCIe generations allow for longer trace lengths. Each generation its own specifications on impedance and maximum trace lengths for different data transfer rates, and these should be closely followed in order to maintain required performance. The exact routing specifications depend on which PCIe generation you are using for your design.

Trace lengths in Gen 1 and Gen 2 both allow RX and TX signal traces to reach up to 21 inches in length, while Gen 3 only allows trace lengths up to 14 inches on these signal traces. Each TX trace pair should only include up to 2 vias, while RX pairs can only include up to 4 vias in order to maintain impedance within the required specification. For traces on a COM Express carrier board sent to a PCIe slot, Gen 1 and Gen 2 both allow maximum trace lengths up to 9 inches.

The differential impedance of signal lines depends on the bus used to connect to your PCIe board. Standard PCBs with differential pair routing typically use 100 Ohm differential impedance. This same standard is used in Gen 1 with the PCI-SIG bus, while Gen 2 and Gen 3 use 85 Ohms differential impedance with the PCI-SIG bus. The COMCDG Rev. 1.0 bus only requires 92 Ohms differential impedance with Gen 1 and Gen 2 PCIe, and this bus is not compatible with Gen 3 PCIe. Instead, COMCDG Rev. 2.0 was devised to be compatible with PCIe Gen 3 and specifies differential impedance of 85 Ohms.

The tolerance on differential impedance values also varies among the different PCIe generations and bus standards. While the values are different for each bus and generation combination, you can find these values in the COMCDG Rev. 2.0 specification.

Keeping the impedance of your microstrip traces within tolerance is much easier when your PCB design software includes controlled impedance routing features. You can specify the impedance tolerance directly in your design software, and your autorouting or interactive routing tool will ensure that your traces are laid out with the right geometry and spacing.

PCIe riser extenders plugged into a motherboard

 

Stackup and Grounding

Typical PCIe boards use a 4 layer stackup with two interior power planes and two signal layers on each surface. Each power layer can be brought to different bias levels, depending on the device requirements. Some designers opt for a 6 layer stackup with two signal layers running between the two power layers. Some guidelines are also available for 8 layer and 10 layer stackups for PCIe boards.

In some PCIe boards with a 6 layer stackup, one of the power planes can be replaced with a ground plane. In both cases, signal traces routed on the inner layers will have better immunity to EMI. You can also route traces with different data rates on different layers. In a mixed signal board, such as in a Wi-Fi or other wireless device on a PCIe card, you can route the RF signal lines on the inner layers and digital lines on the outer layers. The ground/power planes will effectively block noise from reaching the sensitive analog signal traces.

Whichever stackup you use, you’ll need to make sure that the overall thickness of the board matches the standard 1.57 mm (1 mm for PCIe Mini) thickness for all PCIe cards. You’ll also want to pay attention to standard high speed design techniques as PCIe Gen 1 operates at 2.5 GHz clock speed, and the signal speeds only increase for later generations.

Traces routed on a PCB with blue solder mask

 

Pins, Pads, and Breakout Routing

Routing around obstacles and accommodating components and vias on a PCIe board is especially important. Routing to pins, pads, components, and BGA breakout routing should be symmetric. Differential pairs should be tightly coupled throughout their entire length, meaning any variations in one trace due to pads, vias, or components should be mirrored in the neighboring trace. This ensures crosstalk is suppressed throughout the entire length of the pair. Note that this is a good idea in any high speed system.

The same applies to routing breakouts from a BGA or other components. Routing to a BGA, for example, will require a bend be placed in one trace to reach one of the pads. The same bend should appear in the other trace if possible. The pair should also be routed together between neighboring pads on a BGA, rather than routing with pads between the traces.

As the performance requirements of PCBs for computer peripherals continue to increase, designers need all the tools they can find to help them keep up with new developments. The layout and routing features in Altium Designer®, are integrated into a single program alongside simulation, verification, and production preparation features. The ® package helps you ensure that your layout and routing meets PCIe specifications.

Now you can download a free trial of Altium and learn more about the layout, routing, and verification features. Talk to an Altium expert today to learn more.

About the Author

Zachariah Peterson


Zachariah Peterson has an extensive technical background in academia and industry. Prior to working in the PCB industry, he taught at Portland State University. He conducted his Physics M.S. research on chemisorptive gas sensors and his Applied Physics Ph.D. research on random laser theory and stability.

His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental systems, and financial analytics. His work has been published in several peer-reviewed journals and conference proceedings, and he has written hundreds of technical blogs on PCB design for a number of companies.

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