Previously, I posted about designing a simple DC brushed motor controller using a single IC. While it’s a relatively simple board, it will still be transferring a maximum of 4 amps of current if both motors are running at the driver’s full rated current per channel. For a board as simple as this, you could simply look at the trace length and width and use an online calculator (or a little math) to figure out current densities on the traces and see how they would cope with the load. For more complex boards, however, that can get quite tedious very quickly. If you have polygon pours which carry current, a mixture of trace widths, components along the trace, or other complex PCB features, it becomes more difficult to calculate whether the board will be sufficient for the task at hand.
Being able to visualize current density on a copper layer helps you make more optimal design decisions.
This is what I really love about PDN Analyzer: it takes a little bit of work to set up for a complex board, but once you’ve done that, it shines spectacularly by letting you optimize your circuit board for the currents and voltages on it. Even if just for powering a microcontroller or an FPGA, you can use PDN Analyzer to quickly visualize where current densities are too high, or the voltage drop on a trace is exceeding your margins. For less technical stakeholders, it also allows you to quickly create a visual map of the circuit board to highlight potential issues, allowing you to see why you may need to shift the specifications a little (perhaps giving you more board real estate) to ensure the board works as expected.
If you’re new to PDN Analyzer, I wanted to create a board you could download and follow along with to set up the power network and look at the analysis as a way to learn how to use the tool. The Altium documentation contains several getting started examples, however the motor controller project I built is much simpler and allows you to quickly set up the power network for every net on the board, which I hope will allow you to get started that much quicker if you’re pressed for time. There is also the full getting started guide for PDN Analyzer which runs through installation and licensing. Finally, you can also check out the PDN Analyzer documentation.
Before starting PDN Analyzer, I suggest you first add net names to any nets that you will be referencing in the power network design. This makes them much easier to find, rather than having to rely on identifying a net named something like IC2_2!
The schematic of the motor driver circuit as shown in Altium Designer
When you open PDN analyzer, you will start out with a new solution that has a single network to get you started. I highly recommend expanding your PDN analyzer window out a bit larger than the initial starting size to make viewing the network easier.
PDN Analyzer has an unnamed simulation with your single network.
Next, you’ll want to click on the DC Nets button to set up the voltages and specify which nets you’ll be working with.
The window to set up the voltage levels for the nets in your schematic will pop up.
Then, select all of the nets and click Add Selected. If the net you’re looking for is missing, you can click the Enable all nets for filtering checkbox to make them all visible.
The setup I use for the power network on an H-Bridge looks a little odd at first glance, as we want to simulate the current path from the supply all the way through to the ground. Technically, the load is the motor connector, however, for simulation purposes, this isn’t particularly helpful as the current will be flowing through the driver IC, the motor, and then back to the driver IC to go through the current sense resistor—at least with the Allegro A4954 this project is using. To handle this, I’m setting the network’s load to be the current sense resistors (R6 and R9 connected to the CS1 and CS2 nets), and extending the VCC net through each net that carries current to the motor with IC1 and the connectors (J1 and J2) as the series connections between each net.
We described the power flow through our network with R6, R9, and IC2 configured as loads.
For completeness, I’ve also added the voltage regulator as a voltage regulator load, shown as Load 1 in the figure above, despite its low current draw. Adding voltage regulators as a load allows you to correctly simulate current flow through the board. When adding a load, you can set the Device Type to VRM (Voltage Regulator Module) at the top of the Device Properties window, which will then allow you to generate a new network for the regulated side of the voltage regulator. Don’t forget to set the output voltage!
I set the voltage regulator device to VRM, specified the VRM terminals, and set the Vout parameter to generate a network for voltage regulated side.
On the 3.3V net, I have extended the network out to the VREF nets in the schematic using the potentiometer as the series component. I set the resistance of the series component to what might be an in-use value for the pot, and then set the current draw for the bottom leg of the resistive divider to what the current across it would be through the resistive voltage divider. Note that the resistor values are relatively low, as this board was in an industrial environment where EMI could induce voltages on the reference nets and potentially cause unexpected behavior from the motor.
The 3.3V network sources current from IC2, the voltage regulator, and sinks it into R2 and R4, which are the bottom legs of the resistive voltage dividers.
Once the voltage regulator load is on the network, you can right-click it to generate the output network by selecting Add VRM to New Network.
Once you have the network setup, you can click the Analyze button to simulate the network.
PDN Analyzer has a lot of interesting analysis readily available, beyond the great visuals on the circuit board that make reports for clients or management look so great. The analysis it provides allows you to rapidly make real engineering decisions and analyze the design and potential changes that may need to be implemented along with the limits placed on external outputs/inputs.
If you’re working with supplying microcontrollers, FPGAs, RF modules, or other voltage sensitive devices, PDN Analyzer can significantly speed up the process of figuring out whether the trace widths are sufficient for the voltages reaching the sensitive load to remain within tolerance. On this project, however, I won’t be looking at the voltage analysis as I’m only interested in the current moving around the board. It’s a compact design with relatively thin traces for a motor driver that I’m worried could potentially overheat. If I was checking this design manually, I’d primarily be calculating the current capacity trace by trace with an online calculator tool like the one from EEWeb.
With PDN Analyzer, I can analyze the entire board in less time than it would take me to calculate just a couple of traces manually. As PDN Analyzer outputs current densities rather than temperature rise, we still need to manually look at what might be a safe current density. Current density is more practical for making decisions, as factors such as airflow, enclosure, ambient temperature, surface coating, and many others will contribute to the actual temperature rise and ampacity of a given trace in the real world. For a board such as this, I would consider 100-120 A/mm2 to be critically high, as this will lead to about a 30°C temperature rise over ambient in still air on traces of the same size as those on the board. To keep a trace safe, a current density of 60-75 A/mm2 would be acceptable on high current nets, as this should lead to a temperature rise of only about 10°C over ambient.
The tabs at the bottom for each network contain tables of analysis which can be very helpful for ensuring the sanity of your design. These tables are going to be far more useful for the microcontroller or FPGA circuit simulation mentioned above, yet for this motor drive the Visual table is going to allow validation of the design much more quickly. Don’t get me wrong, the tables are really helpful for the vast majority of boards you might simulate, however, for this motor controller we want to be analyzing the actual traces in detail rather than just overall power statistics.
Power consumption tables calculated by PDN Analyzer. Open the image in a new tab to see it clearly.
On the Visual tab, clicking the Current Density button then 2D button will show you your configured network without the ground displayed (the ground mostly gets in the way, but should definitely be checked later on in the analysis).
Most of the traces have high current densities but we can’t make any deductions as the densities are not shown in the units we want.
This is showing the current density as a percentage. Note that the colour spectrum is non-linear. The colour scale is also shown per rail, in this view we have multiple rails visible which makes the 3.3V rail on the left side of the board running vertically look like it’s carrying a similar current level to the motor traces, as they both carry almost 100% of their respective rail’s current density.
If this isn’t the output you’re looking for, you can change the colour scale to still be auto, but set it to ‘Displayed’ instead, which will show actual current densities.
Furthermore, by going to Manual display, I can make it very obvious which traces, or areas of traces are overburdened by my configured 2A per motor loads. The 2A per motor is the maximum that the driver can support, despite mentioning in the previous article that I am driving a 1A motor on each output. I don’t know what this board’s future might be, so it’s worth checking at full current capacity.
My final setting shows the highest degree of red at 100A/mm2.
By changing to a manual maximum ampacity of 100A/mm2, my board starts to look a bit different.
Where have the traces gone?
The black traces are where the current limit is outside of the specified range, and this makes it immediately obvious that there are multiple traces that are undersized. The motor traces would be in danger of overheating and potential delamination at 2A per motor.
Changing the loads in the network to 1.2A, a little higher than my expected maximum load, brings these traces under the maximum limit I mentioned earlier. They will get warm, but not to a dangerous level.
The traces might be gone at 2A but they’re very much present at 1.2A. They will, however, get a little warm.
There is however one point that is still black: around the via for the IC’s voltage supply. This section will need a redesign with a larger trace, or maybe even a polygon pour. To determine what trace width might be more appropriate here, I would turn to the online calculator I mentioned earlier to give me a good starting point. To do that, I need to know how much current is going to be on that trace, and not surprisingly, PDN Analyzer can instantly figure that out by using the Probe tool. On the same Visual tab, you can click Probe and then click on the area of the board you’re interested in.
The location we probed in the VCC net of the top layer is carrying a whopping 1.768A of current.
This tells me I can expect to see about 1.768A on the board, with a 32um copper board, a 0.75mm trace width would be more appropriate than the 0.45mm that is currently present from following Allegro’s recommended PCB layout in the datasheet.
Given the board layout here, and the spacing between the IC pins, a polygon is going to be the easiest way to get more copper to this pin.
The board after adding the copper polygon to the VCC net.
After redesigning this area of the board, all I need to do in PDN Analyzer is to click Analyze once again to see the results of my change.
The copper pour reduced the current density around the IC’s voltage supply and all the traces look fine now.
With the same manual color scale applied, it is immediately apparent that the additional polygon has done wonders for the current density around that area of the board, as you would expect. It is well within the safe margin now.
Now that I have confirmed the current capacity of the traces is sufficient, the ground pours still need to be checked. If you followed along reading the first article where the driver board was designed, you might remember we had some cutouts on the bottom of the board to provide a star-ground for the current sense resistors as recommended in the datasheet. I want to ensure that this won’t adversely affect the current capacity of the board, and on the top side and ensure that the current sense resistors and the power connector have sufficiently wide connections without any restricted areas in the polygons.
Top side of the board after the copper has been revealed.
On the top side, you can clearly see the current path from the exposed pad of the driver IC to the power connector pin. Again, I can use the Probe tool to look at any point on the polygon to find the current density at a specific point of the board.
The hottest point on the top side copper region is only at 16.93A/mm2, which is around one-sixth of the maximum of 100A/mm2.
Now that I’m satisfied with the top of the board, I can check the bottom polygons with the cutout areas.
The bottom side of the board looks all fine as well!
Given the gap in the slot going between the current sense resistors and the exposed pad, it’s not much of a surprise that the current density is well within acceptable limits. Nevertheless, being able to visualize this result is still interesting.
This analysis is just scratching the surface of what is possible with PDN Analyzer. While I’ve only focused on the visual and current aspects here, the tables on the other tabs are worth digging into. I like to check on the Pins tab to make sure that each pin, especially on connectors, has less current flowing through it than the manufacturer’s maximum specifications just in case I’ve selected an inappropriate part, or the current is higher than I had initially expected. In the Vias tab, I like to sort the table by Current Density, which allows me to quickly make sure the highest current densities are within acceptable margins. If the current density is too high, I can quickly add an extra via, or change its size and re-analyze to see if my change brought it to within spec. If you set up acceptable tolerances for voltages or current levels in your network, the net tabs can quickly show you whether the net passes or fails the requirements you’ve set.
Based on my analysis of this driver board within PDN Analyzer, it is probably appropriate to change the values of the resistive divider for the current setting on the driver IC to ensure the maximum current cannot be set above 1.2A. I could also change the trace widths, however 1.2A exceeds my requirements.
I could also add additional vias or copper in other areas that have higher loads.
Try It Yourself
If you have PDN Analyzer, you can download this project fully configured and simulated on GitHub. If you want to follow along and build the analysis yourself, you can download the project prior to adding PDN Analyzer at the point of the conclusion of the previous article from this commit. This will allow you to replicate this simple project and experiment with analyzing a basic motor driver circuit.
If you don’t have PDN Analyzer, I hope the analysis of this simple project gives you an idea of why I fell in love with this simulation tool when it was added to Altium. Whether I’m designing a simple motor controller, powering much larger loads, or have sensitive voltage tolerance requirements for more common circuits, PDN Analyzer saves me so much time on analysis of the layout, and gives me confidence that the finished copper board I receive will perform as required.
About the AuthorMore Content by Mark Harris