Should you plate your through-hole vias in mmWave PCBs?
Recently, I received a question from a designer at a startup wondering about proper use of plated through-hole vias in mmWave PCBs. It got me thinking that I neglected to mention this point in a previous blog post, although space in these posts can be limited. This is a fair question, both when dealing with microwave/mmWave frequencies, and when working with high speed digital signals.
At mmWave frequencies, signals can experience strong reflection and resulting transient behavior as a travelling wave interacts with a via in an interconnect. If improperly sized, a signal can be strongly reflected from a via plated through-hole via, or the signal can strongly resonate. The question regarding use of plated through-hole vias at mmWave frequencies brings up another question: the use of through-hole components at mmWave frequencies. Anyone familiar with through-holes knows that they are a simple solution for routing between layers, but they can create more problems than they solve when working at high frequencies.
Modeling Plated Through-hole Vias in mmWave PCBs
In some ways, plated-through hole vias on mmWave interconnects are much easier to model and understand than digital signals with comparable knee frequencies. With a typical mmWave signal, your signal bandwidth is generally smaller than a comparable digital signal, unless you are working with ultrafast pulses, such as in radio over fiber (ROF). As an example, consider 400G networking; running at this data rate requires using multiple signal lanes operating at 25 to 50 Gbps (16 or 8 lanes, respectively). Modulation schemes (PAM-4 in this case) allow more bits to be packed into a single channel, which sets the required repetition rate in a given channel to a much lower value.
This spreads the bandwidth of high speed digital signals (e.g., with 20 ps rise time) out over about half a decade, whereas a frequency modulated mmWave signal has a much narrower bandwidth. For example, in 77 GHz FMCW automotive radar, the signal bandwidth is only 4 GHz, or only ~5% of the carrier frequency. In terms of analysis, this means you only need to consider what happens with the carrier frequency to a first order approximation.
When modeling plated through-hole vias in mmWave PCBs, one must consider the intrinsic inductance and parasitic capacitance of a via when designing its geometry. The fact that a plated through-hole via has inductance should be obvious—you essentially have a loop of conductor—and flowing current can create a changing magnetic field in the core, which induces a back EMF. However, these vias also have some parasitic capacitance and DC resistance. The resistance can normally be ignored as it is typically much smaller than the reactance of a via, particularly at high frequencies. This means we need to treat a via in an mmWave interconnect as an LC circuit. It has some resonance frequency, and it can create an impedance discontinuity on a transmission line.
Add to this the possibility of a via stub on an mmWave interconnect. The via stub effectively forms a closed resonator, and it will have a resonant frequency spectrum with fundamental quarter wavelength equal to the stub length, and higher order harmonics equal to odd multiples of the fundamental frequency. This effectively forms an antenna that splits off from the via in parallel. When excited at high frequency, the stub incurs some return loss, reflecting some of the incident wave back into the via barrel and along the interconnect. This creates a second source of resonance as you now have incident and reflected waves interfering with each other in the via barrel.
Proper use of plated through-hole vias in mmWave PCBs
If You Must Use Plated Through-holes, Make Sure They’re Properly Sized
This should illustrate two important points in via design for mmWave interconnects and RF signal chains: proper sizing and elimination of resonance. The latter is rather easy; simply backdrill plated through-hole vias should you choose to use them. This relates to the other point regarding through-hole vias, which is the use of through-hole components. The leftover stub on a through-hole component can also act as a floating resonator at certain frequencies. It is best to use SMD passives to prevent these resonances.
The LC resonance in a plated through-hole via is not as important as the impedance discontinuity it creates. All mmWave PCBs should use controlled impedance transmission lines with proper driver and receiver termination. I would advocate using grounded coplanar waveguides (GCPW) on the surface layer. If you must use a second layer for routing, use striplines in an inner layer, and keep these lines on the interior layer below the GPCW ground plane.
Routing between layers with vias requires that the vias be precisely sized such that you do not create any impedance discontinuity along the interconnect. The primary cause of any impedance discontinuity in a via in a mmWave interconnect is parasitic capacitance in the circuit; at high frequency, the via impedance appears capacitive, leading to an impedance dip in a time-domain reflectometry (TDR) scan. If you can resize the via so that the capacitance is minimized, you can treat a via as an inductor out to a higher frequency range, which makes it easier to size and layout RF circuits with microstrip transmission lines.
You can measure the impedance along the length of an interconnect with a time-domain reflectometry measurement
If you use a vector network analyzer, an S-parameter measurement should show flatter insertion loss out to a higher frequency in your interconnect. This shows how losses can be reduced by properly sizing plated through-hole vias for mmWave PCBs. Other steps designers can take involve choosing a high frequency compatible laminate with low loss tangent.
If you do plan to use through-hole vias in mmWave PCBs, you’ll need to use the right routing, stackup, and via design features. Altium Designer® gives you all these advanced RF PCB design tools and many more in a single program. You’ll have a full suite of layer stack, via, and pad design features that are ideal for any application.
About the AuthorMore Content by Zachariah Peterson