Stubs On Transmission Lines—What Do They Do And How Do You Keep Them From Happening?

December 30, 2019 Kella Knack

In other articles we have written PCB Design For Test Structures And Tests Performed, Part 2, and How to Control Switching Signals with Terminations for Best Signal Quality, we have described how to properly account for all the various factors that impact the design of high-speed signals. Within those topics, we’ve noted that stubs along a net may have an adverse effect on the quality of those signals. But, we have not thoroughly addressed stubs, what they do and what you do to keep them from causing problems. This article will discuss this topic, including how stubs behave electrically, their impact on transmission line performance, and whether or not vias can act as stubs.

Note: In addition to our articles, if you do a search for the term “stub” or “stubs” on the Altium
resources blog section, it’s readily evident that the topic of stubs is frequently mentioned when it comes to transmission line design for high-speed applications.

A Little Background on a Big Problem

To begin, a stub is a branch off the main line of a transmission line. If it’s the right length, it will function as a short circuit at some frequency. Figure 1 illustrates the definition of a stub. 

Figure 1. A simple illustration of a typical stub, which is any branch of the main line
Figure 1. A Typical Stub

Figure 2 illustrates what happens when a stub whose length is ¼ wavelength at some frequency is excited by a sine wave at that frequency. In this figure the following behavior is exhibited:

  • The first waveform, which is shown in black, is the signal at the input end of the transmission line of the stub.
  • The second waveform, which is shown in red, is what appears at the far end of the transmission line.
  • The third waveform, which is shown in blue, is the reflected wave as it arrives back at the end of the stub.

Quarter-wave stub behavior showing the input and output of the transmission line along with the reflected waveform as seen by the input
Figure 2. Waveforms on a Quarter Wavelength Long Transmission Line

Breaking this operation down a bit further, the sine wave is launched into the transmission line. A quarter wavelength (or 90° into the cycle), it arrives at the open end. Since there is no absorber or termination at the open end of the line, all of the energy is reflected back to the source without its being inverted. A quarter wavelength later (or 180° into the cycle), it arrives back at the source exactly 180° out of phase with the original signal canceling it out. This shorting of the signal will occur at all frequencies at which the stub is an odd multiple of a quarter wave. Note: Quarter wave stubs are commonly used in RF engineering to create notch filters or band stop filters at selected frequencies. Because digital data paths can see data traffic that ranges from DC to the highest frequency required to create the rise and fall time for that data path, it's imperative that there are no stubs that can short out any of those frequencies. 

Stub Specifics

Figure 3 depicts a clock tree with stubs. It is the same clock tree as that shown in Figure 4 but it has been rerouted so that it has stubs. There are two waveforms for these clock trees and the colors in the waveforms correspond with the colors of the lines in the clock trees.

Circuit showing a clock tree with stubs labelled pink and blue on the main line labelled red and yellow
Figure 3. Rerouted Clock Tree With Stubs

 

The same transmission line shown in figure 3 but modified to not have any stubs
Figure 4. Figure 3 Clock Tree With No Stubs

Waveform of Figure 3 Clock Tree with Stubs exhibiting waveform reversal as the blue wave goes back up to 1 after hitting zeroFigure 5. Waveform of Figure 3 Clock Tree with Stubs

The waveform for the clock tree in Figure 3 is shown in Figure 5. The blue waveform on the right hand side goes all the way to zero and then back to 1. This creates a double clock. Figure 6 is the waveform for the clock tree in Figure 4 but the stub has been removed and, as can be seen, the waveform reversal has gone away.

Figure 6. Waveform for Figure 4 Clock Tree with Stub Removed showing that the reversal is gone after the stub has been removed
Figure 6. Waveform for Figure 4 Clock Tree with Stub Removed

Another Source of Waveform Reversals

The other source of waveform reversals are improperly placed loads. Figure 7 depicts this. At the bottom of this graphic is the “before” and “after” net topology. The reason this waveform is included in this article is that product developers have sometimes assumed that a waveform reversal is due to a stub that they cannot locate. Instead, the source of the reversal is the improperly placed loads. 

Figure 7. A photocopy of a paper containing a screenshot and a hand drawn schematic trying to describe waveform reversal caused by improperly placed loads.
Figure 7. Waveform Reversal Caused by Improperly Placed Loads

Stubs and Edge Rates

As noted in here and many other places, in today’s high-speed products, it’s all about signal integrity. And when it comes to signal integrity it’s all about the speed of component edges. The edge rates of today’s components require tightly controlled interconnects. Lee Ritchey, Founder and CEO of Speeding Edge explains, “You have to worry about the connection going up into the IC package on the die. If it’s not done exactly right, you can have a situation where a stub is created and it’s not always clear that it has happened. You also need to be aware that when you are going from pin to pin, the edge rates are very fast. If they are not taken into account, it’s another instance where a stub can be created.”

In today’s design environment, the biggest challenge is DDR (double data rate) memory. Ritchey notes, “With very high data rate signals, the path has to consist of only two parts—the driver and the receiver. You can’t stop along the way and create another connection because of the path up into the added connection. If you do, you create a stub.”

“Normal address lines go past several DIMMs (dual in-line memory modules). Every path up into the DIMM is a stub,” Ritchey continues.“We are up against the wall because of that. We can’t make memory go any faster. We want it faster but we can’t have it faster. All of the protocols we are using are so fast that you can only have a two point net. That’s why DDR memory has become the hardest part of design. Routing memory is painfully hard. Everything else, by comparison, is easy.”

Vias as Stubs

Occasionally, we are asked if a via can act as a stub. This discussion arises on 2.5 GB/S and higher designs, especially as they relate to backplanes. The reason that this discussion centers more on backplanes rather than on daughter cards is that backplanes tend to be much thicker than daughter cards so the vias are longer.

At the beginning of this article, I described the behavior of a quarter wave stub. For a structure such as a via to function as a stub, it will have to have a length that is a significant part of a quarter wave length at some frequency in a logic signal. The highest frequency in a signal will be the first affected by short stubs such as vias. The most common digital signals that are involved in this discussion are 2.4 GB/S and 3.125 GB/S signals. These signals have a fundamental frequency of 1.2 GHz or 1.56GHz, and a rise time of 150 pSec starting into a transmission line on which vias may be present. Because the preservation of the 150 pSec edge is the primary goal, it is necessary to ensure that there are no stubs long enough to upset the frequencies in these edges. The first harmonic of this edge will be approximately 2 GHz. This has a period of 500 pSec and a wavelength in a PCB of about three inches. A quarter wave stub at this frequency would be about ¾ inches or.95 cm long.

Next, it is possible to compare the length of a via to the quarter wave length of this edge. The backplane thickness in big systems is commonly 0.250 inches, 6.3 mm. This is 1/3 of a quarter wave length or 1/12 of a wave length. The length of the via is still short compared to the signal traveling on it. If the length of the via is on the short side for it function as a stub, what is the via doing that adversely affects the signals? As has been noted many times, vias in transmission lines look like small parasitic capacitors that lower the impedance at the point where they are located, causing a negative or “undershoot” reflection. The approximate capacitance of the 26 mil, .66m diameter holes drilled in backplanes that accommodate press fit connectors is 0.6 pF per 100 mil, 2.54 mm length. For a 250-mil backplane this is roughly 1.5 pF. This parasitic capacitance can be added to the simulation of such a signal path to see what the effect is. In the simulations we have done, the primary effect such a via has on the signal is to increase jitter. When speeds go up to 4.8 GB/S, there is a viable effect on both jitter and loss.

If the parasitic capacitance of this type of via is too large, there are a couple of ways in which it can be addressed. Studies have shown that the capacitance of a via is directly proportional to the area of the cylinder formed by the plating in the hole. There are two ways to address this: decrease the drill size by using a connector such as the Teradyne GBX connector or the newer surface mount connectors, or make the backplane thinner by reducing the parasitic capacitance by drilling out part of the copper in the hole (i.e., back drilling).

Summary

Since stubs of any nature act as short circuits in a transmission line, it’s best to carefully examine all signal paths early on in the design phase of your project. Carefully examining and simulating signal paths  as part of the overall design process will ensure that there are no stubs that can negatively affect the integrity and performance of your final end product.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium or discover more about transmission lines and terminations in high speed design.

Reference

  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.”
  2. Ritchey, Lee W., “Signal Integrity and High Speed System Design,” Two-Day Course. 

About the Author

Kella Knack

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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