Signal integrity analysis and measurements go hand-in-hand
The basics of signal integrity analysis in your PCB can be anything but basic. Simulation tools are great for calculating the behavior of signals in different nets during schematic and layout design, but you’ll still need to take some steps to interpret the results. As advanced as some signal integrity and EM simulation tools can get, they simply can’t compare to the information you can glean from measurements. Whichever method you use to examine signal integrity in your board (you should do both), there are some important steps you can take to analyze the behavior of your signals and identify problems in your board.
Getting Started with Signal Integrity Analysis
Signal integrity analysis begins with simulations at the pre-layout phase. Once you build up your layout, you can use some important post-layout simulations to analyze geometry-dependent signal integrity in your board. At some point, you will need to compare your simulation results with real measurements, so keep your results handy for comparison.
This portion is really about circuit design and component selection. There are three important analyses that tell you a significant amount of information about your board’s behavior.
Transient behavior. Transient responses can also be modeled in the time domain using transient analysis, or you can determine the behavior of transients from pole-zero analysis. This will show you overshoot/undershoot due to ringing, which can then be checked against your design rules.
S-parameters and transfer function. Certain functional blocks in your board can be modelled as multiport networks, meaning their linear behavior can be described in terms of S-parameters at a particular frequency. You can determine the S-parameters from a reflection coefficient in the time domain. You can calculate the transfer function for your network from the S-parameters, and vice versa. Here’s an excellent guide that shows all the mathematics involved.
Noise analysis. Components that exhibit rectification and saturation (diodes, transistors, etc.) will respond differently to noise than they will to an intended signal. This aids filter and amplifier design in the presence of noise as low level noise may experience more or less transimpedance than your desired signal. Add to this the fact that different noise sources can span across the frequency domain (e.g., 1/f noise, shot noise, and Johnson-Nyquist noise), and it can be challenging to address the presence of noise in certain circuits. Examining how noise on signal sources propagates through your circuit can help you experiment with different steps to eliminate noise.
Relationship between S-parameters and a transfer function for a 2-port network
This portion is really about examining how parasitics in your board affect signal integrity. As parasitic signal integrity effects are functions of board geometry, you’ll need to examine the following geometry-dependent signal integrity problems:
Crosstalk. The bane of many designers, crosstalk arises from inductive and capacitive coupling. If you are examining the effects of crosstalk on a victim and aggressor trace, capacitive coupling will only occur when the two are adjacent. Inductive crosstalk is not limited by range, and all traces in your board can couple to each other via the magnetic field.
Transmission line behavior. While you can use transmission line models to examine signal traces during the pre-layout phase, it is best to do this directly from your layout. If your lines are not impedance-controlled, then you will need to examine whether reflections on the line (if any) degrade signal levels at the receiver and lead to a stair-step response with digital signals. With analog signals, this can be more tricky, as you are looking for interference and standing wave formation on the line. However, the right signal integrity simulator can separate the incident and reflected waves, allowing you to examine the behavior of each individually. You can then determine the level of reflection and see if the signal level meets your signalling requirements.
Everything you examined pre-layout! The point here is to check that parasitics do not dramatically alter the behavior of signals in your board. If multiple traces are failing, then your layout will need to be modified. The first place to start is with your stackup and trace geometry.
The exact steps you should take depend on what exactly failed. Strong reflections can result from minor impedance mismatches, producing a stair-step response in digital signals, thus your impedance mismatch must be reduced (ideally, it should be zero). Ringing results from parasitic inductance and capacitance. If ringing produces excessive overshoot, then reducing parasitic inductance and capacitance by the same factor will keep your trace characteristic impedance constant while increasing damping in the circuit, which will reduce the ringing amplitude. The other is to increase damping by adding a series resistor.
Eye Diagrams in Signal Integrity Analysis
One of the most fundamental measurements used in digital systems, particularly in Gigabit networking equipment and amplitude modulated signalling, are eye diagram measurements. Simulating bit error rates in a digital channel requires accounting for noise sources in your board, which are not always known a priori. This particular measurement helps you quantify a wealth of information from a single measurement. You can extract the following information directly from an eye diagram measurement:
Timing jitter. The variation in rise/fall initiation can be seen directly from an eye diagram when you look at the signal crossings during switching.
Signal level variance. You’ll be able to easily see how the signal level varies. This is, in general, some function of the timing jitter plus other random noise.
Intersymbol interference (ISI). This is important in multilevel signalling (e.g., PAM-4) and is rather obvious from looking at an eye diagram. Still, you should perform some basic analysis of your data to quantify ISI and check it against your standards. This will help you determine what level of equalization you should apply.
Average rise/fall time. This is related to the jitter and the average transition between signal levels. You can easily calculate this using the time between the average 90% signal level time and the average 10% signal level time.
Symbol duration. This is the time between your two jitter measurements at the midpoint between signal levels.
If we assume that multiple noise sources in the circuit are uncorrelated (i.e., independent), and that each noise source has zero autocorrelation (this is the case for Johnson-Nyquist noise and 1/f noise), then any averages of our measurements from an eye diagram will converge to a Gaussian distribution. This means we can extract the average signal levels and timing jitter using some basic statistical analysis. If you are working with multilevel signalling, you can apply the average signal level measurements at each level. There are some other measurements you can extract from your eye diagram; take a look at this support article from Keysight for guidance on other measurements.
Eye diagram and statistics for the 0 level. This image was adapted from the eye diagram in Jason Ellison’s recent article on COM.
From here, we can quantify the bit error rate by counting the number of times the signal level falls outside the required noise margin. Since you are normally working with billions of bits, it is easier to calculate the cumulative probability that the signal level reaches the threshold for the undefined region for each signalling level. Since we are generally working with a Gaussian distribution (see the histogram above), the probability that the signal reaches the undefined upper or lower threshold can be calculated easily using error functions. There are plenty of open source programs and online calculators that will calculate this cumulative probability for you quite easily.
When comparing the real bit error rate to the required bit error rate, you can determine whether or not you need a forward error correction technique. With multilevel signalling, you can also determine whether you need some equalization scheme. Dynamic feedback equalization is one scheme that is already useful for 400G with PAM-4, although other equalization schemes are better for reducing ISI in different situations.
The powerful PCB design and analysis tools in Altium Designer® give you a useful starting point for signal integrity analysis with pre-layout and post-layout simulation tools. These accurate calculations give you a baseline for comparing your measurements. You’ll also have access to a complete set of manufacturing planning and documentation features in a single platform.
About the AuthorMore Content by Zachariah Peterson