Using Prepreg vs. Core for Controlled Impedance Routing

Zachariah Peterson
|  Created: December 29, 2019  |  Updated: December 26, 2022
Using Prepreg vs. Core for Controlled Impedance Routing

When I was first learning the finer points of PCB design, my first impression that the core was some type of special material that did not have close resemblance to the other layers. This is not necessarily the case, but designers need to work within the core/prepreg stackup constraints imposed by the PCB manufacturing process. Although you may be constrained as to how the layers in your board are arranged, you can choose which core/prepreg layers you be using for routing. When it comes to controlled impedance routing, especially at high frequencies, the difference between core and prepreg layers as the separating dielectric now becomes an important question.

So how does each type of layer affect controlled impedance routing? Greater control over board impedance requires greater dielectric constant uniformity before considering fiber weave effects. It also requires greater consistency and predictability in the dielectric constant of a board produced after manufacturing. Here’s where you should carefully shop for the right materials for your layer stack when determining where to route your controlled impedance signals on prepreg vs. core layers.

Controlled Impedance Over Prepreg vs. Core

The core is the thick, rigid layer of glass fiber that is typically placed at the center of boards with low layer count. From what I’ve seen, using the word “core” causes some new designers to take the term literally, meaning any design must have a core at the center of the board with other layers built around it. I later learned that this is not a strict requirement, especially as layer counts increase. You actually have alternating layers of core and prepreg, and the central layer is not always a core layer. The important point is that the layer stack is symmetric, regardless of where core layers are placed.

The prepreg material is not produced fully cured and forms the glue between core layers. In a recent project on a 1.57 mm standard thickness board, we used a Rogers core on the outer layers and FR4 prepreg/core in the inner layers; this type of hybrid multilayer board is common (i.e., PTFE laminates on FR4). Cost is a factor here as different materials carry different costs, thus low-loss laminates are generally reserved for layers carrying high speed/high frequency signals.

Generally, the core layer is more reproducible than a prepreg, both in terms of the dielectric constant and thickness as the core material is already bonded with copper. In contrast, the prepreg manufacturer can only specify a dielectric constant range for the raw material; they are not specifying the dielectric constant after assembly, which will determine the effective dielectric constant seen by signals on an interconnect. Some specialty low-loss prepreg laminates can have very wide variations in dielectric constants (beyond 50%).

Pressing and cutting for prepreg vs core materials

Single or Double Ply Core?

Some core materials with different glass weave styles will have significantly different dielectric constants, which also depends on whether a particular core material is single ply or double ply 106 and 106/1080 cores are perfect examples. The dielectric constants for these materials can vary by approximately 10%, which requires adjusting trace widths if you take an existing design and swap between single and double ply cores.

In addition to the number of plies, prepreg and core with the same weave style and porosity will have different dielectric constants. Also, different laminate thicknesses will require different glass weave styles. This is why materials are normally classified in terms of desired Dk range, and many manufacturers will simply call out thickness, weave style, and number of plies you can use for core and prepreg in product sheets. The different resin content and thicknesses of these materials will produce different dielectric constants.

How to Work With Your Manufacturer

Selecting the particular parameters of your PCB materials such that you ensure high yield and reliability is an aspect of DFM that is not discussed sufficiently. My hope is that the above points I've discussed will better prepare you to have a material selection conversation with your fabrication house should you identify prepreg and core selection as an important quality/reliability parameter for your product.

When communicating impedance control requirements on core/prepreg layers, there are generally two ways to specify your material requirements:

  1. It's common to specify the track width and copper weight (thick can be easily converted to a track thickness), and your target impedance value. In this case, the fabrication house will attempt to combine their available materials to hit the performance targets you specify.
  2. If you're instead specifying on dielectric constant and laminate thickness, or specific PCB laminates, you would want to include these points in your fab notes and stackup table. The fabricator may select an equivalent alternative material. If you also need impedance testing, you would then also include the width/copper weight values in your fab notes.

If you’ve already designed your board around standardized laminates your manufacturer has in stock or can get on order, then make sure you specify your material selection in your fabrication notes. Otherwise, your manufacturer could recommend the closest core/prepreg thicknesses that hit your layer thickness and/or impedance requirements. However, not all manufacturers will follow the thickness values listed on a material datasheet and will plan their own press-out thicknesses.

Prepreg vs core dielectric for impedance control

The higher level of dielectric repeatability and standardization of core layers means controlled impedance design is more predictable (i.e., smaller variations in dielectric constant throughout the board) when the core is used as the dielectric. You could also use a core and prepreg with the same thickness for symmetric striplines. No matter how you arrange prepreg and core layers, your layer stack should be arranged symmetrically to prevent PCB warpage after pressing and cooling steps during fabrication. It’s also common practice to mix different materials, such as a high speed laminates with basic FR4 core layers. However, not all materials should (or can) be combined by every manufacturer; some fabrication houses specialize in hybrid stackups and will have the processing capability to mix these materials in your PCB stackup.

Selecting and routing on prepreg vs. core materials is easiest when you use PCB design software with an integrated stackup and impedance calculator tool. The layer stack manager in Altium Designer® is an ideal tool for designing your board with controlled impedance and arranging your perfect layer stack. You’ll also have access to an extensive materials library that contains important data on a broad range of standard materials. You can also specify specific material properties for exotic substrate materials.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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