Keep your signals synchronized with parasitic extraction in your PCBs
Parasitic extraction: the integrated circuit design community must grapple with this task on a delay basis, especially once gate features are reduced below ~350 nm and chips run at high switching rates. The PCB community also has to deal with this idea in order to better design power delivery networks, interconnects with extremely precise impedance, and properly quantify crosstalk and coupling mechanisms. There are a number of 3rd party applications that can be used to extract parasitics from your layout for specific geometries, but the results from these tools are impractical for use in most advanced PCBs.
With lower speed signals and data rates, and in less dense boards, you can usually get away with simply tuning lengths of groups of traces to minimize timing skew in your board and ensure consistent timing in differential pairs. However, with high speed signal traces that require extremely small impedance variations, differential pairs with extremely precise coupling, and high density boards, parasitics can become so prominent that simple length matching is not accurate enough to prevent skew between parallel signals. This is where an electromagnetic solver in your routing tools is required for delay tuning—where signal behavior is considered in the time domain rather than in space.
Parasitic Extraction for Delay Tuning
With PCBs spanning such a large area compared to a typical high-speed integrated circuit, why do we need to worry about parasitic extraction? The answer becomes obvious when we look at edge rates of extremely high-speed signals and the potential for skew to accumulate as signals traverse your board. The time per unit length required for a signal to traverse the board is called the propagation delay or transmission delay (not to be confused with the delay that occurs when gates or flip-flops switch).
If you’re familiar with impedance formulas and transmission line models, then you know that propagation delay depends on the effective dielectric constant in an interconnect. The effective dielectric constant can be determined geometrically using electrostatic or magnetostatic methods. It can also be determined by calculating parasitic capacitance and inductance, which define the wavenumber, signal velocity, and impedance of the interconnect. Geometric methods and parasitic methods are intimately linked and are effectively equivalent.
Delay tuning for multiple signals running in parallel (i.e., any routing standard with multiple data lines in parallel and a source-synchronous clock) requires accurate quantification of parasitics. As these parasitics determine the propagation delay and impedance along an interconnect, the goal in routing should be to equalize the time required for each signal to travel from a driver to a receiver. Because parasitics are geometry-dependent, and real PCBs almost never use sets of parallel traces on the entire board, parasitics can lead to slight variations in propagation delay in different interconnects, and skew in each interconnect must be compensated individually.
This is the essence of delay tuning. No matter which meandering style you prefer to use in your board, parasitic extraction can be used to determine how the propagation delay varies as you apply delay tuning. This involves calculating parasitics as meandering is applied until you reach just the right propagation delay required for skew compensation. With external parasitic extraction tools, this is a time-consuming iterative process, or it involves a number of candidate interconnect designs and some level of experience on the part of the designer. However, there is a better solution that involves an electromagnetic field solver.
Next-Gen Delay Matching with an Electromagnetic Solver
Although you could cobble together a fragmented workflow involving multiple parasitic extraction simulations for idealized structures, you’ll never get exactly the right propagation delay in a real PCB except in two cases. The first of these is the case where you can access a parasitic extraction tool that runs data directly from a layout file or from your Gerbers. A few of these are available, for a price. The better alternative is to use PCB design software with an electromagnetic solver that interfaces with your routing utility such that the propagation delay is determined directly from parasitics as you route your traces.
The best way to take advantage of these capabilities is to simply route your traces according to the rules for your particular signalling standard, followed by applying delay tuning with the assistance of your electromagnetic solver. With the right interactive routing tools, delay tuning features can be easily applied to an interconnect after it has been routed. The use of delay tuning over length tuning is better at compensating skew as your electromagnetic solver calculates the propagation delay for the interconnect as you apply tuning. This leads to more accurate matching between signals while maintaining the desired interconnect impedance.
When your electromagnetic field solver is built into your interactive routing tools, you can determine accurate propagation delay and delay tuning with parasitic extraction.
With differential pairs, your routing techniques become a bit more complex as you should aim for consistent coupling throughout the pair. Symmetry and consistent length help ensure that the maximum level of common mode noise can be suppressed at the receiver. Some lack of coupling is allowed at the driver end as long as the interconnect is symmetric at the receiver end. This is where phase matching should also be used at the source end, although this is really just a variation of delay tuning. Parasitic extraction during delay tuning helps here as well, especially with ultra-fast signals.
The interactive routing features in Altium Designer® now include an integrated electromagnetic field solver that determines the propagation delay as you layout traces. These advanced routing tools take the guesswork out of length tuning and delay tuning. You’ll have access to these automated analysis features, as well as convenient simulation and documentation features, in a single unified design environment.
About the AuthorMore Content by Zachariah Peterson