Routing Differential Pairs in Altium Designer

December 31, 2018 Altium Designer

Blue IC in tweezers

Working with routing tools in your PCB design software can be a huge time saver. When you have a simple board with a small number of components, it’s fine to route by hand, but routing components like connectors or FPGAs with a large number of connections can take a huge amount of time. Automated routing, pin swapping, and part swapping tools make it easy to route all of these connections quickly while still working within standard PCB design rules.

If you’re working with a high speed device, you’ll need to route differential pairs between components if you want to reduce crosstalk and eliminate mode electronic noise in these sensitive signal lines. When you’re working with a large number of components with tight spacing requirements, automated routing of differential pairs can be a huge time saver. All of these features need to operate within your PCB design rules.

Working in a PCB design software package that unifies your routing, layout, and simulation tools in the same rules-driven design engine ensures that your designs will meet the basic rules that ensure PCB functionality. You’ll also be able to define custom design rules that are critical for your application. Other design software packages claim to unify these features, but they still separate these features into different programs or force you to use a third party program to finish basic design tasks.

 

Defining Differential Pairs in Your Schematic

Once you’ve decided to use differential signaling in your device, you’ll need to define which connections on your components will use differential signaling. Getting started with differential pair routing requires defining signal nets in your PCB. The schematic and layout editor in Altium Designer® include net definitions functions, and you can define differential pairs within a signal net. First, you’ll need to select some components that will communicate with each other, place them in your schematic, and define which I/O ports will use differential signaling.

To get started, we’ll look at the schematic below and define the differential pairs we need to use in our board. This schematic contains a Lattice LFXP2-5E-5FT256C FPGA. This component can be found in the Lattice FPGA XP2.IntLib integrated file. For brevity, we’ll only use “Part A” from this , which appears as “Bank 0” on the schematic. Some of the outputs will be sent to a MHDR1X12 12-pin connector, which can be found in the Miscellaneous Connectors.IntLib integrated file.

A simple schematic in Altium

FPGA and a connector in Altium

Note that, in this simple arrangement, we’ve selected specific pairs of I/O pins from the FPGA to connect with the MHDR1X12 connector. The FPGA I/O pins that are capable of differential signaling are indicated with the double-ended arrows on an output pin. We now want to define some of these I/O pins as differential pairs. One of these interconnects needs to be defined as positive and the other as negative. In addition, pairs of connections that are configured for differential signaling must be linked together in a differential pair net.

First, you can specify which connections are differential pairs by clicking on the “Place” menu. Highlight the “Directives” option and select “Differential Pair”. You’ll be able to place a specific symbol on the connections you want to function as differential pairs.

Since we need to define a differential pair net class, we’ll add this net class label to each directive. I’ve defined net classes “D1” for connections C4 and A3, and “D2” for connections F5 and G6. You’ll also need to give each connection its own net label; click on the “Place” menu and then select “Net Label”. Altium uses a particular naming convention for you differential pairs. The positive end must be named using “_P” at the end of the net label, and the negative end must be named using “_N”.

If you double click on the directive symbol, you’ll be able to define classes and design rules for a connection in a differential pair. You can also right-click on the directive symbol and click on “Properties”. This will bring up a menu that allows you to specify a label, classes, and rules for a connection. Here, we will add the “Diff. Pair Net Class” to each pair and assign a class name for this net.

Defining differential pair design rules and constraints in Altium

Defining a differential pair net class

Now we want to add design rules to this directive. If you click on the “Add” button below the rules list, you will see a dialog appear with a long list of design rules. This allows you to specify everything from size and placement constraints to differential pair routing constraints. In some cases, you may want to use different design rules for different sets of differential pairs. Otherwise, you can specify a rule for all pairs in your PCB, or you can use the default rule built into Altium . For now, we will add the default rule to each of the differential pairs in the schematic.

If you click on the “Differential Pairs Routing” rule and click “OK”, you’ll see a dialog appear that allows you to define several routing constraints for differential pairs, as shown in the figure below. Here, we’ll define the preferred width as 10mil, although can enter any value you like. Once you’ve entered the constraints you need for your board, click “OK”, and this design rule will be applied to this connection.

Defining a net class for a differential pair in Altium

Differential pair design rules and routing constraints

 

Routing Differential Pairs in Your Layout

At this point, we can capture the schematic as a layout and route the differential pairs we defined. I’ve defined differential pairs for the rest of the connections between the FPGA and the connector. First, add a new PCB to your project and capture your schematic. You can do this by opening your empty PCB and clicking the “Design” menu, followed by “Import Changes From…”.

An unrouted layout in Altium

Unrouted layout between an FPGA and a connector

This initial layout can be improved somewhat by moving or rotating one or both of these components. Taking a look at this arrangement, it is easy to see that routing will actually be easier if the connector is placed horizontally above the FPGA. If you take a look at this configuration, you’ll see that it will still be rather difficult to route all of your pairs without swapping some of your differential pairs and pins.

While pin and differential pair swapping, you should try to eliminate as many crossovers as possible. One possible arrangement that can be feasibly routed is shown below. Notice that pairs 2 and 3 have been swapped, and pairs 5 and 6 have been swapped. After swapping these pairs, some of the pins within each pair have been swapped in order to keep these pairs from crossing each other.

 Screenshot of new pin arrangement after pin swapping in Altium

New pin arrangement in Altium

Now we can route the differential pairs between the connector and the FPGA. You’ll need to make creative use of vias and routing through the inner signal layers in order to access the inner pins of this FPGA. Note that it is just fine to place each end of a differential pair on separate layers, and grounding vias are not required if a via is used to route one end of a pair between layers.

Vias placed inside the FPGA will need to be microvias; we’ve used 10mil vias with 5mil holes in order to guarantee there will be plenty of clearance; although Altium allows you to specify any via size, this is about the smallest via size you should ever use. You will also need to make sure that your choice of vias and pads will be compatible with your BGA. Vias outside the FPGA will be 20mil vias with 10mil holes as these do not require the same tight manufacturing tolerances as smaller vias.

Once you’ve placed your vias, defined the appropriate drill pair, and assigned each via to its signal net, you can use the interactive differential pair router to place traces between the connector, vias, and pins on the FPGA. The image below shows differential pairs being routed using the interactive tool. The interactive differential pair router places each trace in the pair as parallel as possible within the limits specified in your design rule. Hopefully, you can start to see how the connections are coming together.

Screenshot of new mid-routing with differential pairs in Altium

Differential pair routing in Altium

The final layout between these two components might look something like this:

Differential pair routing into an FPGA in Altium

Final routing layout with differential pairs

If you’re familiar with FPGAs and similar components with high pin density, you’ll know that you will want to use a fanout strategy once you utilize most of the available pins on the component. Note that you don’t have to do this if you are only using a small number of pins: manually placing signals lines into the inner portion of the board is fine in this case. Thankfully, Altium offers an automated fanout tool that can save you a significant amount of time when routing signal traces into and out of an FPGA.

Going further with this design will require length tuning to compensate skew and ensure that the rising and falling edges of signals in a differential pair are aligned. The rising edge of the signal in one trace should coincide with the midpoint of the falling edge of the opposite polarity signal in the other trace within a differential pair. Meandering is one compensation method that can be used to add some length to the shorter trace in a differential pair.

Altium unifies information in your design with your routing tools, ensuring that your next device will function as intended. The integrated environment in Altium allows all your tools to communicate using the same rules-driven design engine. The best schematic, CAD, simulation, and routing tools are exactly what you need to create the best PCBs.

Talk to an Altium expert today if you want to learn more about Altium .

About the Author

Altium Designer

PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

Visit Website More Content by Altium Designer
Previous Article
Working with IPC Compliant Footprint Models
Working with IPC Compliant Footprint Models

Avoid extra design costs from your manufacturer with this IPC Compliant Footprint Wizard app extension avai...

Next Article
From Mechanical Drilling to Laser Drilling of Microvias
From Mechanical Drilling to Laser Drilling of Microvias

Designing an HDI multilayer PCB? Pay attention to the smallest drill size you need for your vias.