Can you spot the orthogonal trace routing in this complex board? Neither can I...
I occasionally see questions on forums, some blog posts, and even application notes that continue to recommend the use of orthogonal routing, usually in 2-6 layer boards. When looking at application notes, I tend to default to Rick Hartley’s advice and try to think about this advice in context. Unfortunately, recommendations in application notes are not always taken with a grain of salt, and they are often applied in situations where they are not applicable.
This article is more about when not to use orthogonal trace routing, rather than how it can be configured in an autorouter or a similar topic. If you’ve worked in the ultra-high speed/high frequency world for a long period of time, then this is most likely not new to you. For the rest of us, there is a temptation to default to old information that is often provided without context. This is especially true of orthogonal trace routing.
Bad Stackups Lead to Bad Routing
I think the first time I saw a recommendation that designers use orthogonal routing was on StackExchange. This website is an excellent resource on many topics, and it is definitely my go-to resource for all things related to software and coding. With electronics and PCB design becoming ever more complex, it is easy to apply recommendations from this site and others without considering context, leading to cases where these design choices cause a board to fail.
I recently had a client looking for some help debugging an upgrade to an older design. The client decided to use the classic orthogonal trace routing recommendation with a 6-layer stackup, similar to the stackup shown below. In this stackup, the two top layers and two bottom layers are signal layers. Traces in these layers were routed orthogonally between ICs, and standard through-hole vias were used for layer transitions.
Don’t use this simple 6-layer stackup with high speed signals...
The experienced designer should already have an idea of what is wrong with this picture. The problem was that the engineer was trying to upgrade the design to use a new MCU that runs at 400 MHz without changing the stackup, and the design inevitably failed. This is not the first time I’ve received this type of question, and I was a bit surprised to hear that this same stackup worked as desired with an older (and slower) MCU.
At this point, the solution should be obvious; design the stackup properly and you won’t have to rely on orthogonal routing to ensure signal integrity when working with high edge rates. As it turned out, this ended up being a power integrity problem, which has less to do with orthogonal routing and more to do with layer arrangement. However, this begs the question: when should you use orthogonal routing?
When is Orthogonal Trace Routing Applicable?
The primary goal in using orthogonal trace routing on adjacent signal layers is to eliminate inductive crosstalk between traces. As a digital signal propagates, it generates a magnetic field, and the switching edges of the signal will generate a changing magnetic flux in the region around the trace. When the magnetic field lines are incident on a closed loop of conductor perpendicular to the loop area, the changing magnetic field flux induces and back EMF in the victim signal line (thank you, Michael Faraday!).
When interconnects on adjacent layers are routed orthogonally (along perpendicular directions), the magnetic field from one trace will always be oriented parallel to the conductor loop formed by a victim trace on the next layer, effectively eliminating direct inductive crosstalk. While this description is technically correct, it is overly simplistic and does not account for other important aspects of a real PCB stackup and layout. The primary problems involved in using orthogonal routing relate to switching speed, decoupling, and defining a reliable return path. Rick Hartley discusses some of these important routing and stackup aspects in a recent interview.
Despite the lack of inductive coupling, there is still capacitive coupling, even with the small intersecting area between traces. If you haven’t properly designed your return path, the electric field between signal layer 1 and ground (see the above image) can couple back to signals in layer 2 simply due to a potential difference, producing capacitive crosstalk. The impedance seen by the capacitively coupled signal is lower when the signal edge rate is faster, producing a stronger current pulse in the victim trace.
Advanced designs like this won’t use orthogonal trace routing.
At lower edge rates, you probably won’t notice capacitive crosstalk, regardless of whether orthogonal routing is used. It will still happen, but it might not be sufficiently large to break through the noise margin of any components connected to victim traces. At low speed, inductively coupled signals see lower impedance, thus you would want to route orthogonally on adjacent signal layers in order to minimize inductive coupling. Working with low edge rates is one instance where orthogonal trace routing in adjacent signal layers is appropriate.
For the rest of us, we’re usually working under a nanosecond in terms of edge rate, which requires careful shielding/isolation between signal layers, a carefully engineered return path, and ultra-stable power delivery. It all hinges on designing the right PCB stackup.
The routing and layer stack design features in Altium Designer® are the go-to choice for creating your board and your layout. The rules-driven design engine provides return path checking and other important DRCs as you create your layout. You’ll be able to design top-quality PCBs for any application. You can also simulate various aspects of signal behavior with the post-layout simulation tools in Altium Designer.
About the AuthorMore Content by Zachariah Peterson