High speed SerDes design goes far beyond computer peripherals
The challenges in high speed SerDes design filter right down to the PCB level and are all about backplane/daughtercard design, transmission line layout, selecting proper equalization schemes, and much more. This even gets down to the fundamentals, where stackup and power integrity become critical when driving transmitters and receiver ICs. If you’re designing a PCB as part of a SerDes channel for a networking environment, we’ve compiled some important design points you should follow when creating your product.
The Signalling Environment in High Speed SerDes Design
Each bandwidth iteration in SerDes design in a data center environment and other networking applications has been driven by a doubling in the number of links, doubling in data rate across a single link, or both. At some point, the clock speeds involved in high speed SerDes design are becoming so fast that signal integrity problems become more prominent. This places the difficulty in properly decoding data primarily on the receive side of a SerDes channel, and on physical channel design.
Whether you are using a 2-level signalling scheme like non-return to zero (NRZ), or you’re working in an environment that uses a multi-level signalling scheme like 4-level pulse amplitude modulation (PAM-4), your primary PCB design challenges include the following:
- Impedance discontinuities. Any time there is an impedance discontinuity, you have a reflection, which reduces the signal level seen at the receiver. Bends and corners can generally be ignored; the important impedance discontinuities in SerDes designs are connectors and vias.
- Attenuation. Signals degrade as they travel along the PCB, which limits allowed trace lengths in high speed SerDes design. This will also affect which equalization scheme to use (if any) in your particular application.
- Other noise sources and fiber weave effects. With SerDes channels designed to operate with such fast rise times and high frequency modulating baseband signals (e.g., PAM-4), signals could excite unique noise sources, depending on the fiber weave and trace dimensions.
For something like PCIe 3.0, you’ll be using LVDS or another differential signalling methodology. This suppresses common-mode noise, but it places greater emphasis on eliminating skew during routing. Breakouts should be carefully designed so that phase matching at the transmit side is minimized (i.e., delay tuning). This is part of a complete controlled impedance routing strategy.
Connectors and Vias
Connectors and vias in your PCB are particularly important when designing a SerDes channel. Whether you are using a PCIe add-in card or you are transmitting data over fiber, you’ll have to send data through a connector. Eliminating any impedance discontinuity requires accurate termination. This becomes much more difficult when we look at what happens in multi-level signaling, where signal margins are much tighter. Accurate S-parameter extraction is critical, as you need to correctly model connectors in order to design appropriate impedance matching networks. This will help minimize losses and maximize useful link lengths. Take a look at this recent article from Jason Ellison for more information on examining connector and backplane impedance profiles.
Connector impedance spectra are extremely important in high speed SerDes design.
Vias are also quite important and should generally be minimally used on higher speed links. At the fast rise times used in high speed SerDes channels, you’ll start encountering some of the same problems seen in mmWave PCBs. If you’re not in the HDI regime, check out this article for some guidelines on working with plated-through hole vias in such high speed links. The high knee frequencies of digital signals brings problems squarely into the mmWave domain, so it is appropriate to follow some general guidelines from designers in this realm.
Regarding attenuation, you’ll need to properly model dispersion in your substrate, particularly with digital signals. Dispersion in your PCB substrate generally acts like a low pass filter, and attenuation produces greater signal degradation and distortion in higher speed digital signals as the knee frequency is larger. This extends the signal bandwidth to higher frequencies (~50 GHz at multi-gigabit data rates that will soon be common in data centers). To reduce losses, their’s no shame in using an alternative substrate material that is optimized for low loss at GHz frequencies.
The level of attenuation in your board, and the frequencies at which attenuation occurs, will determine the type of equalization you need to use at the transmit side, receive side, or both sides. SerDes channels running at higher data rates are now using feed-forward equalization (FFE) and distributed feedback equalization (DFE) at the receive side, as well as feed-forward equalization at the transmit side to provide pre-emphasis. The type of equalization required for your board will depend on whether your channels are insertion loss-dominated or return loss-dominated within your particular signal bandwidth.
Other Noise Sources and Fiber Weave Effects
I know that the term “other noise sources” is ambiguous, but it is difficult to anticipate all sources of noise as SerDes ASICs are still quite sensitive to environmental changes. Temperature is a major determinant of jitter, noise floor, and sensitivity in these components. In addition, a propagating digital signal can excite a forced resonance in pores in a PCB substrate (the fiber weave effect), as well as cavity resonances due to parasitics in the interior of the board. Using conformal coatings is one way to combat EMI from the substrate edge and tailor your PDN impedance spectrum. Using a tighter weave is sufficient to increase the fiber weave loading resonances above the knee frequency, although this is only a temporary solution, as rise times are likely to continue decreasing.
Follow the above advice and your SerDes signals will remain strong
The signal integrity points addressed here all contribute to intersymbol interference (ISI). You can overcome some of the impedance-related challenges in high speed SerDes design by modeling your channel directly from your schematic. If you can obtain test connectors for your system and extract the S-parameters with a vector network analyzer, you can then determine the right termination scheme to suppress reflection over the largest possible bandwidth. I’ll look at this particular point in an upcoming article.
The interactive layout tools in Altium Designer® are ideal for many high speed applications, including high speed SerDes design. These tools are designed to automatically check your layout against your design rules as you create your board. With the pre-layout and post-layout simulation tools, you can take steps to ensure signal integrity in your design before moving to manufacturing.
About the AuthorMore Content by Zachariah Peterson