Eye diagrams in electronics were something of a mystery when I was first learning about digital electronics. How can this simple diagram tell you so much about the performance of one device? It wasn’t until I started designing my own systems until I started to realize the significance of an eye diagram.
Signal synchronization in high speed digital devices relies on accurate switching measurements from digital ICs. There are a number of factors that affect signal switching times, and a bad estimation can increase bit error rates in your device. In devices without redundancy, higher bit error rates could bring your PCB to a standstill.
Signal Rise/Fall Times and Skew
A digital IC has some output capacitance and characteristic impedance, which creates a delay during switching between on and off states. The signal rise and fall times are normally approximated as being linear, but the actual rise and fall times are exponential, similar to what one would measure in a simple RC series circuit.
This linear approximation is appropriate at lower switching speeds, where the switching period is much longer than the equivalent time constant associated with the rise/fall time. A linear approximation tends to underestimate the switching time. Another approximation is to take the switching speed to be the time required to transition between the low end of the on state and the high end of the off state.
Unfortunately, both of these approximations can underestimate the appropriate rise/fall time for a digital signal. This creates problems when choosing the appropriate switching speed and synchronizing signal nets.
The effects of signal switching and the skew it creates are two-fold. First, it leads to time-of-arrival errors for signals transmitted through successive ICs. Different ICs can produce slightly different output pulse shapes, and the output pulse can change depending on an exact stream of digital pulses. This creates different reference times between signals, which then can create a problem for a designer when synchronizing high speed circuits.
Second, the exponential rise and fall times during switching can result in the output voltage falling within the noise margin or the undefined region. This increases the bit error rate if the one attempts to drive the PCB at a data rate that is similar to the effective RC time constant.
SMD integrated circuits
At data rates higher than ~100 Mbps, skew should be reduced by using a forwarded or embedded clock in your PCB. Signals are routed in differential pairs in most high speed designs in order to reduce crosstalk. This requires precise skew compensation between the positive and negative legs of trace pairs in a differential signal net. Gbps data rates or higher may only allow a few picoseconds of skew before signal degradation becomes a major problem.
Effects of Board Substrate and Parasitic Capacitance
Simple simulations can take account of skew in digital signals by considering the conductive traces floating in a vacuum. A better simulation will take into account the presence of the substrate, which creates parasitic capacitance between neighboring conductors. This parasitic capacitance can be treated as a parallel capacitor, which increases the total capacitance of a given trace. This then increases the effective RC time constant and exacerbates skew.
Parasitic capacitance only increases further as the interconnect density increases. These circuits have closer spacing between traces, resulting in higher parasitic capacitance. Trace widths need to be properly adjusted to ensure that traces can be appropriately impedance matched during design.
In multi-layer PCBs, the epoxy resin and glass weave in PCB substrates also has an effect on skew. The weave pattern will almost never align with every trace due to PCB manufacturing limitations. Instead, the weave and trace will be arranged with a certain angle between them, and this angle will impact skew by creating a phase delay. The lateral offset between the weave pattern and a trace also affects skew.
In the time domain, this affects the propagation delay for signals in a given trace. Skew in these situations is normally quantified in units of ps/inch. Longer traces will accumulate a larger skew, and this skew can reach several picoseconds for moderately long traces. This greatly increases the chances of signal degradation in devices operating at Gbps. High speed laminates are typically used to compensate these signal degradation problems in multi-layer PCBs.
Mismatched traces on a PCB
Timing skew due to length or propagation delay mismatches is usually compensated by meandering traces. A signal net with mismatched trace lengths can have all of the trace lengths matched to the longest trace in the net. Meanders need to be added to the shorter traces in order to increase their length.
So how can you ensure that your routing strategy and layer stackup can properly account for skew? Altium Designer 18.1 provides you with advanced routing and simulation tools that can help you avoid signal integrity problems. Now you can download a free trial and find out if Altium Designer is right for you. If you want to learn more, talk to an Altium expert today.
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