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Length Matching in High speed Buses

Altium Designer

| Created: September 28, 2020

With ever increasing speeds in high speed data systems comes a couple of PCB layout challenges. High speed busses like DDR, VME, PCIe just to mention a few can all reach data transfer speeds that require strict timing with very tight tolerances, thereby leaving very little slack in the PCB layout. Join us in this webinar to learn why it's imperative to match track lengths in high speed data systems and differential signals. You’ll see how to properly define PCB length matching and time delay constraints, and how to effectively route high speed signals in Altium Designer®.

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About Author

PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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