Length Matching in High Speed Buses
With ever increasing speeds in high speed data systems comes a couple of PCB layout challenges. High speed busses like DDR, VME, PCIe just to mention a few can all reach data transfer speeds that require strict timing with very tight tolerances, thereby leaving very little slack in the PCB layout.
Watch this on-demand webinar to learn why it's imperative to match track lengths in high speed data systems and differential signals. You’ll see how to properly define PCB length matching and time delay constraints, and how to effectively route high speed signals in Altium Designer®.
Here are some key points covered in the session:
Why is it important to match track lengths in high speed signals?
Length matching and time delay tuning in high speed buses and differential signals.
How to set up high speed PCB constraint rules from the schematics or PCB.
How to tune single ended and differential tracks.
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