Ethernet: IEEE 802.3 PHY Chips for Data Link Transmissions

Ethernet connects computers and their devices to wired networks spanning the globe. It is a collection of standards describing both the physical layer and the software, or data link, layer to transmit information across cables. Ethernet uses cable and local area networks to transmit packets of information via hubs, switches, and routers.

Ethernet is part of the Open Systems Interconnection model (OSI model) of computer communications systems. It describes the first and second layers of the OSI model which include the physical layer and layer 2, also known as the data link layer. A sophisticated arrangement of protocols make up the remaining layers in the OSI model. The protocols delineate roles and responsibilities for organized transmission of infinite amounts of data. This is the data we use in our daily lives for everything from banking and bill paying to entertainment and content generation.

The physical layer is implemented by a PHY chip. The PHY is the physical layer that is the electrical hardware acquiring, processing, and transmitting information along pathways known as the information highway. A PHY chip is an integrated circuit comprising design blocks that describe how each bit of the transmission will be treated while moving through the part. Below we look at three PHY chips designed for use with Ethernet protocols.

Ethernet was First Developed in 1973 for University Computers

Development of Ethernet began when university departments wanted to communicate and share knowledge using new technology called microprocessors. Intel released the first microprocessor, the 4004 in 1971, a small single silicon chip able to move information via addressable and controllable data streams across telecommunications cabling. Access to silicon able to process vast amounts of data provided this new medium for storage and dissemination of knowledge. Universities and corporate think tanks were first adopters. Information formerly generated over months or years was now produced within hours. Early adopters were eager to share knowledge generated on single computers and development of a network to do so ensued.

Robert Metcalf developed the first physical prototype for Ethernet development in 1973 while working at Xerox Palo Alto Research Center. At that time, many network protocols were emerging and Ethernet was based on a packet-switching wireless radio network developed at the University of Hawaii-Manoa, called ALOHAnet. Over the last four decades, Ethernet developed concurrently with silicon and with operating systems becoming the recognized standard for many network communication systems.

First Ethernet prototype developed by Robert Metcalf in 1973 Found on the Smithsonian’s website collection of American History

Defining Characteristics of Ethernet IEEE 802.3

Today PHY chips are available from component vendors to support Ethernet and its complementary protocols within the OSI layers. There are over 50 protocols following development of higher-bandwidth microprocessor capabilities over the past 40 years. The IEEE put together a working group of industry users that collect the standards that define both the physical layer and the data link layer that defines Ethernet.

Below is a glossary of common terms used when discussing Ethernet.

Data link layer: The second layer of the seven-layer OSI model of computer networking.

ENDEC: A device which acts as both an encoder and a decoder on a signal or data stream, either with the same or separate circuitry or algorithm.

IEEE 802.3: A working group and a collection of IEEE standards produced by the working group defining the physical layer and data link layer’s media access control (MAC) of wired Ethernet.

GMII: Gigabit Media Independent Interface. An interface between the MAC device and the physical layer.

HP Auto MDI-X: Automatically detects the required cable connection type and configures the connection appropriately, removing the need for crossover cables to interconnect switches or connecting PCs peer-to-peer.

LAN: A computer network that interconnects computers within a limited area such as a residence, school, laboratory, university campus, or office building.

MAC: Media Access Control. A sublayer that provides flow control and multiplexing for the transmission medium. The MAC sublayer and the logical link control sublayer together make up the data link layer.

MDI: Medium Dependent Interface. The interface (both physical and electrical/optical) in a computer network from a physical layer implementation to the physical medium used to carry the transmission.

MDI-X: Medium Dependent Interface Crossover. A variant of Ethernet over twisted pair technology that uses a female 8P8C port connection on a computer or other network device to connect pins 1 and 2 (transmit) on an MDI device to pins 1 and 2 (receive) on an MDI-X device.

MII: Media Independent Interface. The interface (both physical and electrical/optical) in a computer network from a physical layer implementation to the physical medium used to carry the transmission.

OSI: Open Systems Interconnection is a conceptual model that characterizes and standardizes the communication functions of a telecommunication or computing system without regard to its underlying internal structure and technology.

PHY: The physical layer of the OSI model and refers to the circuitry required to implement physical layer functions. A PHY connects to link layer device (often called MAC) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.

QFN: Quad Flat Pack. A surface mount integrated circuit package with “gull wing” leads extending from each of the four sides.

RGMII: Reduced gigabit media Independent Interface. A standard that uses half the number of data pins as used in the GMII interface.

RMII: Reduced Media Independent Interface. A standard which was developed to reduce the number of signals required to connect a PHY to a MAC.

RX: Receive. The hardwired location of data arriving into a component.

SMII: Serial Media Independent Interface. A serial bus defined for Ethernet family of 802.3 standards employing a lower pin count for transmission.

TQFN: Thin Quad Flat Pack.

TX: Transmit. The hardwired location of data leaving a component.

UTP: Unshielded Twisted Pair. A type of twisted pair cabling.

WAN: A telecommunications network or computer network that extends over a large geographical distance/place. Wide area networks are often established with leased telecommunication circuits.

Parts to Consider for Use in Ethernet PHY layer

Vendors use information from the standard to develop PHY chips. These parts typically integrate processors for encoding and decoding, clocks, and indicator drives commonly used in Ethernet systems. Below are three parts suitable for the physical layer when developing Ethernet.

Texas Instruments DP83TC811R-Q1 Low-Power Auto PHYTER^™ 100BASE-T1 Automotive Ethernet

This is an AEC-Q100 qualified Ethernet transceiver useful in the automotive market. It sports three MAC interfaces with low transmit and receive latency and is configurable to three I/O voltages making it compatible with most embedded systems. The part includes a pseudo-random binary sequence frame to allow transmission without the need of a MAC. TI offers a diagnostic toolkit including integrated ESD monitoring.

The DP83TC811R-Q1 device is an IEEE 802.3bw-compliant automotive PHYTER^™ Ethernet physical layer transceiver. It provides all physical layer functions needed to transmit and receive data over unshielded single twisted-pair cables. The device provides xMII flexibility with support for standard MII, RMII, and RGMII MAC interfaces.

Found on page 1 of Texas Instruments DP83TC811R-Q1 datasheet

The part is available in a 36-pin VQFN package. It is qualified for use in the automotive market for applications in the backbone networks, the gateway and body control functions, and for long-distance transmission of data.

Microchip KSZ8041 10/100 Ethernet Transceiver with Extended Temperature

This is a 10/100 Ethernet transceiver able to support a variety of media independent interfaces at robust speeds while minimizing power consumption. The part detects cable alignment allowing interface with systems sporting both cross-over and straight-through cabling.

The KSZ8041TL/FTL are single supply 10Base-T/100Base-TX Physical Layer Transceivers, which provide MII/RMII/SMII interfaces to transmit and receive data. These devices utilize a unique mixed-signal design to extend signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. Micrel LinkMD^® TDR-based cable diagnostics permit for identification of faulty copper cabling. The KSZ8041TL/FTL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10Base-T/100Base-TX/100Base-FX applications. The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100Base-FX support for fiber and media converter applications.

Found on page 1 of Microchip Micrel KSZ8041TL/FTL Product Brief

The part comes in a 48-pin, lead-free TQFP package. It is useful in applications such as printers, LAN on Motherboard, games consoles, internet protocol TV, IP phones, IP set-top boxes, industrial Ethernet, and automated industrial control.

Maxim Integrated 78Q2123 10/100 Fast Ethernet MicroPHY

This PHY chip is offered in a very low profile footprint with integrated features that allow cable detection, sophisticated coding/decoding, and clock recovery. It is compatible with several categories of twisted cable.

The 78Q2123 and 78Q2133, MicroPHY^™, are the smallest 10BASE-T/100BASE-TX Fast Ethernet transceivers in the market. They include integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The MDI is connected to the line media via dual 1:1 isolation transformers. No external filter is required. Interface to the MAC is accomplished through an IEEE-802.3 compliant Media Independent Interface (MII).

Found on page 1 of Maxim Integrated 78Q2123/78Q2133 MicroPHY^™ 10/100BASE-TX Transceiver datasheet

This part comes in 32-QFN or 32-TQFN packages and is intended to serve the embedded Ethernet market. It works well for applications such as game consoles, broadband modems, printers, set top-boxes, and audio/visual equipment.

Ethernet PHY chips may be used for prototype development of systems from home GPS circuits to sophisticated industrial circuits. Our website lists a number of Ethernet PHY chips which may be found using our part discovery engine. If you are laying down tracks on your PCB, take a look at our 3D model library to integrate a working model into your layout.

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