Errores comunes a evitar en el diseño de fabricación y montaje - AltiumLive 2022

Julie Ellis
|  Creado: February 3, 2022  |  Actualizado: August 26, 2022

Los fabricantes de placas de circuitos y los proveedores de servicios de fabricación de productos electrónicos suelen ver cómo se repiten los errores de diseño más habituales década tras década. Estos errores abarcan multitud de temas, desde discrepancias en la documentación, lo que ralentiza la producción, pasando por propuestas imposibles debido a diseños que no son físicamente fabricables, y hasta problemas con las pruebas. Presentaremos un archivo con los problemas más frecuentes y debatiremos el porqué de algunos de ellos, así como las opciones para corregirlos en el futuro.

Aspectos destacados de la ponencia:

  • Cómo elegir los materiales para crear una placa de circuito.
  • El valor de la simplicidad en la creación de placas sostenibles.
  • La importancia de entender la máscara de soldadura.
  • Ejemplos de cómo utilizar el diseño para evitar problemas en el futuro.
  • Discusión sobre los errores a evitar en el diseño y la documentación.

Recursos adicionales:

Transcripción (en inglés): 

Julie Ellis:
Welcome to Common Fab and Assembly Design Errors to Avoid the scope of this presentation will include advanced project planning to avoid errors in advance, Common Design Errors. I've highlighted some of the most difficult ones with three asterisks just to give you heads up on those. We'll talk about some of the process descriptions so that you can understand why design features actually cause errors once they get to fabrication and assembly. I'll list some possible corrections to choose from and then I'll go through several recurring errors relating to panelization, testing, spacing aspect ratio and some common design for assembly violations which also include via protection.

So when starting a new printed circuit board assembly it's really good advice to consider the complete project, so nothing falls through the cracks, everything is already designed and ready to go to fabrication and or assembly. It's a lot of times customers come to me and they've already done their Gerber files, the design is done and now purchasing or the project manager wants to take cost out of the project. Well, let me as assure you that the easiest way to take costs out of a project is to design for efficiency before you even start routing your circuit board traces, and before you even think about where your tooling holes in your box builder going to go.

So once we have determined how complex the assembly is the complexity of the assembly and the number of IO and everything will pretty much determine how difficult the printed circuit board is going to be to fab. And fab complexity is dependent on layer count, thickness, dimensions the different types of Via hole structures and the lines and spaces. Normally the smaller things get the more difficult they are to process and the tighter tolerancing we need with enabling equipment, and we have tighter design rules because the process tolerances like a plus or minus three mil become very big compared to small features.

So we need to also consider surface finishes and how we're going to achieve good interconnectivity, including good solder joints we'll consider material for the printed circuit board based on the frequency, whether the final application has a high temperature or high shock or high voltage environment. And we'll try to use the most simple and lowest cost material as possible that we'll still meet the requirements of the whole assembly.

Now, when we're getting down to designing the printed circuit board, the most difficult complex component pad size pitch and density drive the design complexity and the stack of the printed circuit board. So complexity of the stackup will include number of laminations which will all include different drillings in each lamination, and they will affect the processes and cost to the complete PCB.

So once you have a really complex printed circuit board or one device that's really driving fine features, a really good piece of advice is to go back to standard design rules for the rest of the circuit board, once you've found out that device, and once you've gotten outside the edges of that device. So another thing that should be considered in the printed circuit board design is what kind of VF protection is needed for vias in pad or thermal vias during soldering. And what this means is if we have vias that are drilled within solderable pads, our assemblers don't want the solder to flow through the via holes when they're going through assembly. So VIPPO, which is called via in pad plated over also known as non-conductive epoxy filled vias used to be approximately 30% more expensive or a cost add or on the top of the original cost of the printed circuit board.

But because we've invested a lot of equipment and improved our processes, that's gone significantly down to at least half of that. So the PCB assembly technical difficulty should drive the designers to consider which fab houses and which assembly sites can actually meet the customer requirements. And based on those, try to pick groups of those ahead of time so that you can work with them on the design guidelines and how they would want to fabricate the product and also how the assemblers would want to run the product down their surface-mount lines or through their wave solder machines after they go through surface-mount, for example.

So use fabricator and contract manufacturer design guidelines based on the site that you're going to use in the end for manufacturing and then consider fab panel utilization, which we'll discuss in more detail later or Array Assembly Panels or raise for utilization, and whether they fit within the assembly maximum size format. And then consider assembly requirements on the printed circuit board such as minimum spacing between components and PCB edges, rails for conveyance down the line, stability of the array, do we have a really thin board like a 32 mil inch thin board that there's one heavy part on it such as a battery, that's going to actually weigh the part down on the conveyor? Or do we have an oversized requirement that is limited by the surface-mount assembly platforms such as solder paste printers.

And then two other things to consider are, are we designing test board that we're only going to build five test boards and just use them in the lab? Or are we designing NPI boards are quick turn prototypes for a product that is eventually going to go to mass production in a lower cost build region? If we are going to mass production in a low cost region such as Asia, then the whole design should be designed in accordance with Asia capabilities and not our quick turn capabilities here in the United States. Lastly, we need to design for excellence, this includes design for fabrication designed for assembly and please remember to design for tests, so that you get enough test coverage. Follow the KISS principle, keep it as simple as possible so that it's easy to build, easy to put together, easy to test, easy to repair.

The point of all of this is that we don't want a bunch of gobbledygook that we're throwing over the wall from the designers to the manufacturers and having a hard time once we get into actual manufacturing. So speaking of DFX including DFS which is the design for tests, I've worked for four different contract manufacturers and I've consulted to a few, and I have been on the floor at every one of these companies where a customer has come in, where in the electrical test room and the customer is going well, why can't you get better test coverage? What's wrong with your equipment? And when I talk to contract manufacturers about this, whether it's sales, engineering, project managers, they all agree with the same thing. If you want to get full test coverage on your component at ICT or boundary scan at the assembly level, you have to make room for those test points on the printed circuit board and make sure that you've got the test points you need. And that they're big enough to be accessible by whatever equipment that you're going to be using for test.

So when we're trying to plan an assembly and a printed circuit board, think outside the board and down the assembly line, if we have kind of an oddball shaped board like this, that has a cutout corner, and that has parts over hanging in different areas, we really need to consider how we're actually going to assemble this before we even lay it out. And so how will it convey down the assembly line? How many PCBs are going to be on this array for surface-mount assembly? Or are we going to put one up and use pallet? And if we do use rails and put it in a panel, is it going to kill our material utilization at the fabricator and increase our costs?

Also, do we really need a rail on say this is our leading edge, can a vision camera read the incomplete reading edges or do we actually need a straight edge coming if we convey this part from left to right down the assembly line? And how are we going to support these parts during assembly? Or is this going to go on after the fact and be a hand place component which also gets expensive? And then lastly, once this assembly is complete is there going to be continuous shock to any over hanging parts such as these two if they don't have any support in the final box bill? We need to consider all these things when we're at the initial stages of the design to prevent any really bad calamities, either in assembly or for long term reliability in the environment.

So one thing that we can do is work with our... Well the correction and what we need to do for at single board is work with both our fabricator and our assembler to determine whether we do need to add rails to this part and what are the minimum rails that are needed so that we can try to achieve the optimum number of these pieces up on an 18 by 24 inch fabrication panel, which is a standard worldwide fabrication panel size. Now the volume production shops also have alternate sizes, some going up to 21 by 24 is a common alternate size, and then there are many cuts both bigger and smaller than that 21 by 24. And then there are some specialty shops that can actually do things that go into airplane wings that are as tall as the people working there. So that's why it's so important that you figure out where you can actually have this product built, if it has any special requirements before you go through all the design and then find out nobody can build up for you.

So this is just an example of rails for assembly and this one I picked it, it was a bad quote from a contract manufacturer where to book the business and to go as fast as possible. It's common for anybody receiving a printed circuit board Gerber file for "a single unit" regardless of how it'll end up going into production later because that's always going to give us our best price. We can see if we quoted this on a little bit bigger panel, we might be able to get one more row up if we don't have these rails for assembly, but the best way to assemble this is to really pick a two up and then put rails on two sides so that we can convey these down the assembly line this way.

And the machines can grip the rails on either side, most contract manufacturers need a minimum of five millimeters, which is approximately 200 milliinches clearance on either side of a bare printed circuit board to convey down their surface-mount lines. So that can be in either in the form of rails or it can also be in the form of having clearance of components on the edges of the printed circuit board. And that's up to you to decide whether you have enough room to do either. So fab panel utilization is the largest cost factor in volume manufacturing because the material gets to be a significant cost of the unit price. So this shows a typical fabrication panel, it's not to scale obviously but if it's an 18 by 24 inch panel, we typically need one inch all the way around for our own tooling and our verification coupons.

So this is our typical fabrication panel, we have our own tooling holes and there will be multiple tooling hole sets within this panel as we go through the processes. And then we also have to retain areas that are represent these are coupons that are actually duplicated, are similar representative of the structures within the circuit board, so that we can do validation of copper plating, dielectric thicknesses and things like that, that's once we're done with our finished product. Now you'll find out a lot of times that if you're trying to optimize your material utilization there are few like two tens of an inch play here and there, depending on the fabricator. So if you're really tight, go to the fabricator that you plan on working with and request their help to plan your array or your panelization so that you can optimize that and get the biggest board size based on the requirement that you need.

This is just a quick example of excellent panel utilization, but in this case we've increased the board length to 11.5 inches, and based on that we can no longer get two more in the X direction, so we just reduced our material utilization to 50%. Here's another similar example, but instead of increasing the length we increase the width by adding rails and again, we can't get these two up and we have just reduced our material utilization significantly. Sometimes what a fabricator will try to do is move this one over here and then rotate this one 90 degrees to put it sideways like this, and usually the way we find out about it is if we have a really high speed circuit and some parts work and others don't because the weaves on the fiberglass are actually rotated 90 degrees out.

So we normally do not try to rotate panels like this and if we are, we would have to auto rotate pieces like this. If we are we would have to review it with a customer first. So this is another example a lot of high speed circuits are trying to avoid the weave effect of the signals going up and down over the knuckles where the bundles of glass cross in the fiberglass cloth, that's a tongue twister, isn't it? And so a lot of customers will actually rotate these at like seven to 11 degrees, but that also takes up space so that affects our material utilization if the boards are already towards the limit of material utilization for a fab panel. So these are just the basic rules for standard capability, I don't want to kill you with death by PowerPoint by going through all of these in detail, because we'll discuss some of them in the future, but this is a good slide for reference.

So we need to pay attention to aspect ratio within our printed circuit board, the pad diameters we need big enough pad diameters so that we can meet the rules, your requirements for classes two or class three annular ring. And pad diameters are always classes two and three are always based on the customer design what we can achieve, not what is required on the fab drawing. So if you require a class three annular ring, then you are going to have to increase your pad diameters by at least three mil over a class two annular ring, that's by design and there's nothing we can do about it because we don't change our fabrication processes to achieve classes two and three, except that we add more are plating for class three requirements. And a lot of the difference between the two is that for class three we have to do a lot more inspections.

So another thing that we pay attention to for capabilities is edge lines and spaces and some and fabricators still because of the level of equipment they have, they can't edge under three mil lines in spaces. So if you're doing something that is really advanced HDI work, make sure that the rules that you're getting are from a known supplier who can actually create that kind of product. Non conductive epoxy filled vias which is called VIPPO is another added process that we should pay attention to. I think when I did this presentation or this slide originally, not all shops had non-conductive epoxy filled vias based on their capability, but most suppliers have this now controlled impedance lines and spaces affect our designs and we have to test these. We also have to put coupons on our panels and then minimum drill hole to copper is a big feature that I'll discuss later.

So just for a matter of perspective of human hair is about 2.5 milliinches to 3.5 milliinches inches or 60 to 90 microns, and a 5.9 mil bit or 150 micron mechanical drill bit is approximately the diameter of two human hairs laid side by side. So when we're talking about milliinches here, we're talking about really small things. And another interesting thing about this slide here is about five years ago, the majority of fabricators over in China would not do any six mil mechanical drill bits, and this is because the small diameters are really fragile high speed spindles are required. The feed rates are about 50% of the standard drill diameters, the drill of life is 300 to 600 hits instead of 1200 to 2000 for a bigger drill, and we can't resharpen these drills, so it's significantly more expensive to drill these holes over in Asia, and there's still a very limited number of suppliers who will drill a six mil mechanical drill in high volumes.

So make sure that if you have this requirement and you have to drive this requirement that you are getting approval from your supplier and the design rules and the stackup, because we also need a smaller than 10 to one aspect ratio for a small drill like this. So some of the design violations that this is one that caught me off guard when I first started working for TTM about 6.5 Years ago, because it's never on design guidelines so we now put it in our design guidelines and it normally comes up under really big BGAs that have laser micro-vias, and so they have all these big pad fields. Now, this is what the expanded copy looks like we've got a four mil micro-via on a 10 mil pad, which means a three mil annular ring.

And then they're all cleared copper because they're not touching this plane. Well, what these donuts of copper clearance they are really difficult to process. And so we have minimums for these donuts, this minimum distance from pad to embedded or embedded pad to copper that is larger than the minimum line width space that we give you for those same layers. So pay attention to this especially when you're designing a stacked micro-via board with a lot of columns and rows that are under a BGA. So in this typical example, these layers they might allow three mil lines in spaces, but we're looking at a minimum requirement for these donut clearances as five mil lines in spaces and make sure that you route your boards for that and that you also simulate your high speed circuits for that. Now in extreme cases where we don't have enough room, please talk to the applications engineers at your fabricator if you really need something a little bit smaller than that, And then we can go to the site and engineers can evaluate and probably give you a waiver for an advanced capability.

So that's another thing when I'm speaking, I'm speaking to standard design guidelines. We can always achieve better capabilities than what I'm showing here, but we don't want you to do it if you don't have to because they can potentially reduce our yields and increase our costs, which we will pass on to the customer. Now why do we have to have bigger spaces, bigger clearances in this BGA field? The reason is because the way we handle this plated layers is we already have base copper foil and we're going to drill the holes, and then we end up plating up our circuits. Well, for us to achieve these little donut clearances here, we actually have to put dry film on them which resist the plating and the dry film in little donut shapes does not stick very well.

It's kind of like going in a swimming pool with baby Band-Aids on, and when these don't stick well we end up exposing that copper to plating and it plates up. And then when we go into etch it doesn't etch down enough and we end up with shorts. So this is for a plated layers what I'm explaining for these donuts, I'd like to go into a little bit more detail what this is showing right here for us to achieve a trace with let's say, this is a four mil trace. We have to protect it with dry film, let's say this is an inner layer we're going to protect it with dry film. And then we go through the copper etch line which actually etches off the adjacent copper, but this is done by conveying this into the screen through copper solution or copper etching solution.

And what happens is these spray come down like this, and they just start etching farther and farther and farther until we get down to the base laminate. But so we never get straight lines here, we actually etch under the dry film and we get a trapezoidal shape. And so for us to accommodate this and make sure that we get a wide enough line after all this happens, because it tends to shrink, we actually have to make our dry film resist larger than the line width that we're trying to achieve in the end. But then that resist is covering up a lot of our space, so if we've got two lines that are next to each other we increase this resist size we've just reduced our trace width. And the same thing happens here which means that little donut being protected is actually... It's hard to adhere to that small space.

Now, another thing that I always ran into was minimum drill to copper or drill to metal requirements. Nobody really talked about that even though it is an IPC specification, and this is out of the IPC 2221, we require for mechanical drills a minimum drill to copper of the edge of the drill hole as drilled to the next uncommon trace of minimum eight mils. This is because we have imaging risk misregistration front to back of two mil lamination layer to layer registration of plus or minus three mil and the drill tolerance of plus or minus three mil just on the size of the drill hole. So in some cases we can go down to seven or six and a half. I really should have changed this to seven because I don't like to see this or take this on behalf of any of my sites because it can get too risky.

So this is something that we really need to watch out for, and one of the other things that causes problems that we'll go into on one of the next slides is your finish hole size, that shows up in your design software is your finish hole size but it's not the drill bit diameter, which is drilled larger. So what I'm saying here is if this drill hole is supposed to finish up at eight mil, we're actually drilling this hole at 10 mil, which that extra two mil annular ring is actually going to reduce this drill distance by two mil. So we need to add two mil to achieve that bigger drill because our drill hole is here, not the finish hole size. So most customers don't understand for any or not most, a lot of customers don't understand that if we give a minimum drill to copper on any through-hole component that's not a via hole that's specified as plus zero minus finish whole size, we are actually going to require 10 mil minimum drill to copper rather than eight mil minimum drill to copper.

And as board get more complicated, more dense we want more vias, we want thermal vias closer together and we have rules for drilling, but when we put circuits really close together, we also have to consider what the application is whether it's high voltage, we don't want the circuits so close together, or whether the material can actually tolerate the shock of being drilled with drills really close together. And so we have to pay attention to other things not only drill to copper, but drill to drill and what minimum spacing we have between these drills. And one of the reasons that we don't normally consider when we have drilling is that in this photograph, I'm sorry it's not bigger. This is a drill hole so there's a drill hole wall here, a drill hole wall here and this is the laminate. And what we're seeing here is the fiberglass weave bundle going in the X Y direction.

And this is actually the bundle, the individual fiberglass threads that are being cut facing us in. So these are the bad ends of this fiberglass bundle as it's shown sideways. And what happens is when we drill through these holes, these bundles get separated and then we go into plating, the plating solution the first one the electro is copper is very fine, and it actually can plate up into these bundles, and so this is actually metal. If we have our drill holes the next drill hole over here is very close, then you can see that we've reduced that distance by 3.15 mil for class three on one side, and then if we have wicking on the other side, then we've reduced our distance our clearance from metal to metal by six mil.

So if we have holes that are 10 mil apart and they're not the same net by IPC class three, they could technically be only four mils apart by IPC class two they could actually be only two mils apart if we had four mil wicking on either side on the adjacent holes. So that's something to pay attention to when you're really trying to decide whether you want to put those uncommon net so close together.

Now in small spaces, minor adjustments have major impacts in two dimension, we already talked about that if we've got a bunch of parallel lines and we have to increase the dry film on top of those parallel lines so that we can achieve those lines, then we reduce the spacing between those lines just because we're taking that space. So an example of one that combines both lines and spaces, or what we can etch for copper and minimum drill to copper is this example. Basically the whole wall to copper is only 7.05 mil and what we're saying is if this is our drill hole, the edge of this drill hole to this copper is only a 7.5 mil, that's what our clearance is it's okay. We can increase it out here but in the case where we have adjacent drill holes, if we increase these to achieve that minimum eight mil drill to copper, then this sliver which is only 3.5 mil now that sliver is going to be 1.5 mil when we increase these diameters of these clearances. So what we need to do in this case is reduce these slivers in order to meet the two other design roles.

So we spent a lot of time trying to fix the problems we created when we tried to fix the problems we created, and the more knowledge we have about the design roles and how one design role and one process affects the next process and on and on throughout the processes, the more we can prevent these design roles causing problems that we need to fix later. This is an example of spacing, there we use a lot of BGAs right now, ranging from anything from 1.0 millimeter, all the way down to 0.4 millimeter down to even smaller than that, most of what I focus on is going to be half millimeter and up or 0.4 millimeter in some cases for our more advanced sites. So in this example, we have 0.8 millimeter and 0.65 millimeter BGA pitches and the rules that are working here.

So this really handy dandy calculator that's in the middle of creation by Richard Dang, a great engineer at TTM technologies who does all kinds of PowerPoint presentations and great Excel work. He created this for us for the bigger BGAs, so we can see we've got a 0.8 millimeter BGA. We're assuming that the board is no thicker than 70 mils thick so that we can get a 10 to one aspect ratio, meaning we can use a common drill bit size, which is 7.9 mil and we're going to use a 20 mil pad give it a good class three pad even though we've said as class two. Well, we can see that we've got plenty of room for everything here and it's fine on the external layers. Same thing with 0.65 millimeter pitch, and I'm bringing this up I've got a reason for this is it looks okay on the outer layers we've got sufficient annular ring.

We have hole to copper 8.55 millimeter or 8.55 mil we're good. But when we go to our inner layers and try to run one trace between these pads, then we run into problems on the 0.65 millimeter pitch BGA. We can see here that we've got plenty of room drill to copper but in this case we only have seven mil drill to copper if we're trying to run a trace between these pads. And so on a 0.65 millimeter pitch part, please work with your fabricator to determine whether you have enough room to achieve a mechanically drilled design or if you have to go to laser micro-vias. So the correction for the 0.65 millimeter pitch part is either to use laser micro-vias which then we can go down to six mil drill and 12 mil pads which gives us a lot more room here or we can use an oddball drill, I call it oddball because I had never seen it before until I saw TTM San Jose using this to preclude this problem of drill to copper.

If we use this drill then we end up achieving our minimum eight mil drill to copper. And if we are here in North America and sites don't typically use that 7.1 hole as long as the board is not too thick to violate their aspect ratio requirements, which we'll talk about next we can use a six mil drill, which is actually five mil bit. So this is... And the reason I bring this up is 0.65 millimeter pitch is really hard a lot of times, a really big device it's hard to fan out using mechanical drills because of the drilled to copper spacing. Once we get down to a half millimeter pitch parts it requires a really, really special highly advanced mechanical drill shop to actually fan out half millimeter pitch parts using a mechanical drill.

So this was actually a reference design from a major OEM, a major component manufacturer that was specifying five mil finish through-holes on 10 mil pads, and I threw all the layers and this part that I worked on happened to be two mil thick. So the aspect ratio is not bad, but most companies will not drill a six mil mechanical drill on a 10 mil pad because it's just really, really tight. And technology is advancing toward that stage, but it's not standard middle of the road technology yet. So if you have a half millimeter pitch part and you want to use 10 mil pads with a mechanical drill, so you can drill all the way through those pads then check with your circuit board supplier to make sure that they have the capability.

So that kind of design from component manufacturers happens often because I don't think everybody understands that there's a difference between the tolerances and aspect ratio requirements for mechanically drilled holes, which can go through a lot of layers and laser micro-vias, which generally are blind holes and they're very shallow going from one layer down to the next layer. It's always an outer layer when we start or an outer layer down to a third layer, if this is an actually outer layer structure. So the aspect ratio on a printed circuit board is the ratio of the overall board thickness being drilled to the minimum drill whole size. And the reason we have aspect ratio is because the bigger the hole is in a thick board, the easier it is for us to maintain consistent plating in the whole walls so that we can achieve the minimum required plating for either class two which is eight 10th of a mil in the hole wall or class three plating which is one mil in the hole walls.

So for through-hole, we'd like to keep it for real standard technology, less than 10 to one for a six mil mechanical drill though, it has to be lower than that like maybe 0.65 to one you would have to check with your fabricator, but for a laser micro-via, we need an aspect ratio instead of less than 10 to one, it has to be less than 0.8 to one or 0.75 to one. And what that means, how that translate is the drill diameter, which starts up here actually has to be bigger in diameter than the depth of the thickness of copper plus the dielectric being drilled. So whenever we see a really small hole trying to go through a lot of layers and ending up on a lot of layers, then we really need to pay attention to how we're actually going to build that particular stackup up.

So laser micro-vias are not through-holes as a rule, but mechanical drills are, on the other hand though mechanical drills can be controlled depth tolerance so that if we have a bigger diameter hole that needs to be a deeper via, we can do a bigger diameter through these with a mechanical drill, but there will be some depth tolerance associated with this. Now this is a project that just came to me recently, it's an existing design, it didn't have this via here but they were having some problems on layer three and they wanted to add laser micro-vias from layer three to four, but we can see that this dielectric thickness is really big. So I had to write back to the customer and say, "Well on an internal layer like this, yes we might be able to do it but we wouldn't want to, because it violates the aspect ratio."

It's just a really uncoordinated stackup if we do this, and so we would have to have a 14 mil drill to be able to achieve this, which the reason I say it would be awkward stackup is because then we can't stack these on top of this big drill, because there's no way for us to effectively solid copper plate this to stack the other micro-vias on top of it. When we have stacked micro-via structures, we require that the internal structures that are getting stacked upon are always solid copper plating and that's a special process. So the other problem with this is if we do reduce the dielectric in order to meet the aspect ratio required for this three to four drill, then we are going to have problems with our controlled impedance lines, because they're already extremely slim. And when we reduce our dielectrics for high impedances such as 120 Ohm here, we have to increase our line widths.

So this means that if we add this drill, then we're going to lose our controlled impedance signals on layer three. And that's some of the trade off that we need to do, one advantage of the stackup is that adding this drill is not going to cost us another lamination cycle, because we're already having to laminate the drill structure layer three to layer 10. And then we can just add a laser micro-via into that layer three to four. So I'm getting into some of the common design issues that I see in assembly, and when I see a solder joint that looks like this and compared to these pins here, this is the top of the device obviously, and the solder didn't wick up.

Normally when solder does not wick all the way up or does not wick and sufficiently up into from the bottom of the pin to the top of the board, and doesn't meet the requirements for depth of solder. It often is because the pin through the layers is connected to too much copper, and in the process that copper is just soaking all the heat up away from the solder and the inside hole wall. So there are rules per IPC 2222 the sectional design standard for rigid organic printed boards, and basically what it says is if you have a drill hole like this, and you need to solder any of those layer you need to solder it. Then you need to add thermal reliefs around this so that the drill hole wall, isn't just seeing solid copper all the way through up and down the hole through the layers. Now another problem that assemblers run into is tombstoning. What happens is there is more thermal mass on a pad that is embedded in a ground plane than there is on an individual pad that is cleared.

So in this case the red is copper and the aqua is copper clearance on the layer, so you can see the solder melted here cause the part to pop up that's called tombstoning, and the way to prevent that is to either make both pads embedded in the plane or do something to clear this pad out by adding thermals. So this is an example of how instead of the pad is embedded in the plane, thermals are added here and this was actually found in a real life assembly design rule check or DFM by a customer at their contract manufacturer.

Understanding solder mask is a really big issue that it seems really simple, the purpose of solder mask is not really to provide electrical isolation between the copper and the circuits from the environment it's actually to prevent solder from flowing from one pad to another and shortening circuits out during solder flow that or reflow that's why it's called solder mask. Touch up can be done and usually when solder mask is touched up, it looks ugly like your three year old painting her toenails. And that a lot of people will complain about workmanship because they think it's going to cause a problem or a quality problem. And that's just the way solder mask is when it's flubbed, it's flubbed but that is acceptable by IPC. And another thing is, in this case I added this picture because if the pads are so close together that we cannot process to effectively hold a solder mass down between these pads then we are going to request gang relief, which means we remove all the solder mass down between the pads.

And you can see there in the real photo, there actually is the solder mass clearance just going around this whole pad area, but not protecting the individual pads, and obviously the contract assemblers or your assembly line does not prefer that because they would rather have that solder mass down bridging, but solder between these pads, but it's not always possible because of space restrictions. These are just examples of how we can protect our via holes because via protection is a really key critical thing that I work with all the time when I'm designing printed circuit boards for assembly. So solder mass webs and dams should be designed between solder pads to prevent solder thieving. What solder thieving is, if this is a hole here if we apply solder pace to this pad and we put the component on and we reflow it, if there's no solder mass dam a lot of that solder is going to also follow the copper path and go right down into the hole.

That can cause problems because it ends up with low copper on your pads, but it also can end up with copper or I'm sorry, low solder on your pads, it can also end up with low solder or solder escaping down through the bottom of that board and into and forming solder balls that can actually dislodge and cause electrical shorts later. So we do everything we can to try to prevent solder from going down vias that are either adjacent or vias and pad, which we'll discuss in a few minutes such. So another method of doing this is to plug the vias and then maybe coat the sides with solder mask on both sides or another method of protecting the via and adding solder mask dam, so that when this is soldered here and this is soldered here we don't end up with some of that solder going down this hole.

We actually create encroached solder mask, which is we take the drill hole diameter, plus six mil and that's and we design our solder mask opening at that size. And that way it slightly encroaches over the pad, but it's small enough that if it's encroached in here, it makes this solder mass dam not opening actually wider. And what we're trying to do is create as wide of a solder mass dam as we can so that we don't have the baby Band-Aid problem where it peels downstream because it's so narrow. So some of the common violations we see are things like we can see that this is a component pad but it's got via holes in these corners. We need to make sure that we protect those and there are as we've discussed, there are several ways to do it, but that has to be planned by the printed circuit board fabricator not by the assembler.

And, but if you're trying to figure out what is best for the assembler, work with him while you're working with your solder board fabricator to determine what your options are and which ones you choose. Now, these are actually component vias and pad or these are other component vias and pad these really need to be filled or plugged or something done with them. And same with this example, we've got vias and pad here, what we don't know in this example is or what we can't tell unless we're looking at the Gerber files. We can assume that these are covered with solder mask, but tinted solder mask is like taking wall paint and rolling, using a roller to roller it over a hole without anything in the hole. What's that hole going to do when you bake it? Air could expand inside the hole and pop open.

So normally we would request to fill those holes, if these are covered with solder mask on both sides of the hole, the last thing that we can do which is great for assembly but like I said, it's more cost to the customer and to the project is to go ahead and use non-conductive epoxy fill with copper cap plates. So your pads even though they have via holes drilled in them, they look just like your surface finish of the pads over here that don't have holes in them. So I'll go back to the VIPPO, I've got a few slides on copper plating relating to that but this is just an example of how we have copper defined BGA pads with dog bone plugged and mass vias. So we've got the copper pads, we have the solder mass clearance so these pads are copper defined, we have solder mask clearances around them, and then we have the holes that are connected to them by we call these dog bones, but we've actually pre-plugged these holes and then coded them with solder mask.

Where we run into problems is on designs that have solder mask open on one side, because it needs to be soldered to a component and closed on the other side to prevent that solder from flowing down and causing a short on the bottom side of the board. And that's the example where I'm saying, I've labeled this thermal vias are a process nightmare, and what I'm talking about is whenever we have DPAK or surface-mount, this is a TSOP, we have these devices and they actually have via holes in them that are being used for heat escaping, they're being used for thermal management. The body of this part needs to be soldered to this pad, and we can't have solder mask plugging these holes.

So, but because we don't want that solder mask going through the... Or the solder piece going through the board then there's solder mask on the bottom side. And this is kind of one of my nightmares that we really have to work carefully with the fabricators to make sure the process can achieve some sort of plug here so that we can not lose all our solder down the via holes, but still have good surface finish inside the via holes and good solder joint on here and no shorts on the other side. As I was looking at this design this was a really good design it's... Whenever I'm looking at designs I look for vias and pad because I'm worried about solder mess or via protection, and then I also look for things like, do I have via pads that need to be protected with the solder dam that are too close to the adjacent pads?

What I like to see is a minimum of nine mil in this case is I was just visually bomb targeting this, the smallest distance I could find here was this pad here, then when I blow it up we've actually got 11 mil from the via pad to the edge of the component pad. We can easily hold a solder mass dam here without having to use the solder mask encroaching that I discussed on a previous slide. So this is a really clean design that way with the exception that they had to have these thermal vias. So like I said, unprotected thermal vias may result in solder starvation of balls. And what I was just showing here is the Gerber file layers, on this side the vias are open on this side they were supposed to be coded with solder mask is what I was trying to show here.

So let's make that assumption, so the corrections in this case are to partially plug the via prior to solder mask and or to use non-conductive epoxy fill. So getting into VIPPO, this is something that we don't all just intuitively know when we're working with our fabrication suppliers about creating stackups. We call the copper weight on the internal layers and a lot of times we call the copper weight on the external layers, but we can see here the half ounce copper relates to six tenths of a mil thickness, but the half ounce copper on the outer layers ends up being two mil thickness. How does that happen? Well, it happens because after we've put all our layers together and laminated them under high temperature and pressure to use the pre-pregs to glue all the four layers together here, we drill the holes and we plate them with copper.

Well, for us to be able to plate them with copper, the holes we actually use the top and the bottom layers as the anodes in the plating tanks, and we plate copper on the top and bottom layers at the same or larger rate than we are plating the copper in the through-holes. So that's how we ended up getting two mil copper plate in the hole walls or on the surface when we started with half ounce foil, and we're only plating eight tenths of a mil on the hole walls for class two or one mil for class three. So that's just something to pay attention to so that when you see this in your stackups, you understand why half ounce copper here doesn't relate to six tenths of a mil over here.

Okay. So, this is a micro section depiction of the outer layers, we have the laminate material, we had our base half ounce foil, then we add the copper plating to the surface, and then actually we had protected our surface that we did not want to plate up. And then we removed this resist and then we etch the rest of the circuitry. so here's our circuitry goes down like this and then this foil is removed well, the difference between... And this is for any plated layer whether it's a layer two to three micro-via layer or whether it's an outer layer in like a stackup that is layer one to 10 only with a drill hole from one to 10, this just shows a micro section view of what a plated layer actually looks like. Here's our base foil and here's the plating in the whole wall and here's the copper plating on the top.

Now, VIPPO it adds actually another layer of plated copper, because the way we do this process is we have to drill these holes by themselves initially then with those open holes, we plate those holes then we squeegee all that film material into the holes, then we planarize and then we go back and we drill the rest of our holes, so when we do this VIPPO process, we're actually adding an extra plated copper layer to this panel surface before we go in with our second drill and plate cycle. And so therefore what we're ending up etching is much thicker, and when we etch thicker copper we have to increase those lines in order for us to achieve that depth of the etch for thicker copper. So whenever we have VIPPO it's difficult if we already have a fine pitch BGA design and the design's been running, but then we add another part and we decide to add VIPPO under that original design we have to increase our spaces on everything by half a milliinch.

So this is a design error that I see frequently, in this case there were solder mass divine pads with VIPPO, and so you can see the little dimples for these holes that actually have vias holes in them not all of them have holes. So what happened here is the solder mask openings on the solder mask layer were all exactly the same size as the pads or actually they were designed as the same size as these solder mask openings which are smaller, but the fabricator in this case thought, "Okay, I need the clearance for these pads." So they added the regular clearance to some holes and not other holes because they weren't defined that some of them needed to stay the original size, which would've been these, these are actually the solder mass defined holes.

And so we ended up with two different pads under the same device. So whenever you have solder mass defined pads, they're not going to be solder mass defined across your whole board make sure that you specifically design or define the solder mass defined pads on your fabrication drawing to your fabricator so that they pay attention to how they treat their solder mask artwork layers when they're fabricating. So this shows all the files required for fabrication, which include the Gerber files and all the layers, the silk screen layers via plugging layers anything that's special drill files, the net list files. We really want the net list because when we do our tooling, we do have to make modifications like for the film compensation. And we like to take our Gerber files and go back and compare them to your net list Gerber files.

We also compare our net list file, we also compare your initial Gerber file to the net list to make that you didn't submit data with any errors. So we do catch errors at this point every once in a while. So it's good to provide the net list with your Gerbers and then we need the fab drawing. We we prefer valor ODB files over Gerber files, we can receive either or and both, but we prefer the valor ODB files they're easier for us to tool our information on and we can take check plots in ODB form but that's not necessary. So the elements for a PCB fab drawing are the title block and part number and revision, sometimes the revision doesn't match that of the Gerber file and a lot of times the part number is slightly off of the actual assembly. So we always have to be careful with our numbering system and that everybody understands the numbering system for the fab versus the assembly and that the rev of the fab drawing may not be the same as the Gerber file revision, because sometimes we need to make a change to one or the other but we don't want to rerelease both documents when we don't have to.

So at both fabrication and assembly, we have to be really careful of our part in revision numbers, so we want fabrication notes they specify are we building this in accordance with IPC 6012 class two? Or are we building in accordance with a mil spec or an automotive specification? We need the mechanical drawing with dimensions, and we really want to see how big the board is on the fab drawing, because that's our first point of contact for deciding the... This fab drawing is the first document that we're going to use to kind of do a rough check with how big is it? How many are going to fit up? Which factory has the capabilities for the technology required on this?

And so to tell you the truth, I really hate it when customers embed their fab drawings and their Gerber files zip packages, or their Gerber files and I have to use a Gerber viewer to find their fab drawing. If you can include it in the packages of PDF, it really helps a lot of people. So we also need the layer construction showing the stack up the layers, dielectric thicknesses, what material we want, controlled impedances and things like that and we need the drill table so there are a lot of victims of incomplete or missing fab drawings because PCB sales and customer support and assemblers and contract manufacturers, everybody that has an asterisk here may or may not have a Gerber viewer. So if you're asking a salesperson to go quote a job and you only give them the job and the Gerber viewers so they can't read a fab drawing to see what the requirements are they can't even figure out which one of our sites, we've got 19 sites they can't figure out which site to send it to.

And so if you give us that fab drawing, it makes it so much easier for receiving inspectors at the contract manufacturer routing operators, please give us that if you can and otherwise this is what documentation looks like when assemblers receive information from customers. So this is in the fab notes check your work, these are some fab notes hall of shame. And we put these in because they're pretty funny after final plating, planarize the high power pads on both sides with a surface finish of 63 micro inches and 0.005 TIIR max, the edges of the high power pads and traces shall be smooth and free of sharp edges. What in the heck does that mean? Barrel misspelled, plating through-holes to be 0.6 mil minimum thick and copper?

Well, that violates IPC requirements for class one and two, which is 0.8 mil minimum. One ounce copper, no hole plating anywhere all sizes are finished diameter. So that's interesting I guess it's just a two-sided board with tooling holes, maybe that one isn't so bad. Layer two is ground plane, planes misfill, board side coupled, should it be broadside coupled instead? Clearance from existing copper and should not be placed under surface-mount devices, so that one's kind of a cute one. Finish gold plate outermost layers greater than 99.5% purity, 200 plus or minus 25 nanometer thick.

Now in printed circuit board fabrication. There's no way we are ever going to have that plus or minus 25 nanometer thick tolerance, because in most cases we are trying to plate to meet the minimum allowable in the place that's most likely to plate effectively, to make sure that we are meeting the minimum requirements across the total surface. Vendor must run auto silk to break silk screen from vias in pads, I'm not sure I've ever seen auto silk. Include three global tooling hole unplated, I guess that's not so bad except Global's misspell. And remove silk screen from solderable surfaces, do not clip but remove the illegal legends.

I think those are kind of funny, so I thought I'd share them. Now, this is just an example of a good fabrication drawing it shows the stack up, the drill holes, we've got our layers, our copper thicknesses. This shows our dimensions, it shows overall thickness here, and it's got good fab notes here. So this is a second page of the requirements for complete fab drawing, which includes a drill table showing all the drill structures, because those are really important in creating the stackup. These are common TQS that we see all the time to date, I have never seen a Gerber file of a new design go through our front end engineering and come out without a TQ. So electronic data and data package discrepancies are real common, like there's no fab drawing or we can't read board files that are submitted as Gerber files instead of 274X or ODB++

I mentioned number two already, the ODB and Gerber files don't match so the customer has to tell us which one we need to use for fabrication. Another common one is that the fab print and Gerber data have discrepancies, the dimensions shown on the fab drawing don't necessarily match the Gerber file, and we should never start fabrication without having every single discrepancy approved by the customer to tell us which one to choose. We should not be choosing that as a supplier. So another common one is that the drill hole counts do not match the number of drills between the fab drawing and the Gerber or ODB data.

Other ones are print dimension do not match the drill data. We already talked about that one, electronic data and package discrepancies. If you have known net list violations such as intentional opens and shorts, please provide those in your documentation because otherwise we find those in our net list check and they come up as errors to us and we can't assume whether they are exceptable or not. Another one that makes it kind of tricky for us is when they're single ended and controlled in differential line and pins lines on the same layers that are exactly the same dimensions it's hard sometimes if the single ended lines are pretty close to each other, they look like differential pair and we don't know which ones are which, so please be more direct in specifying those. And array drawing for assemblies normally need to be created and approved and we can't go back and put individual pieces into a multiple up array or add rails to them after they already been through fabrication. So this needs to be done at the initial stages of prior to start fab.

Another one is when back drills are required, there's something missing such as not stating, in this case this is a through-hole that part of it is going to be back drilled so that the signal is only going this far instead of all the way through the board which could create some sort of antenna for a high speed signal like on layer two. So in this case, we really have to have the layer that we do not want to be cut specified, because that tells us how deep we need to drill. Other things are, this is a control depth drill after lamination we have variances in our circuit board thickness and the control depth drill has a little bit of tolerance. So sometimes we have control depth drill tolerance that is less than plus or minus five mil, which is the standard or we're just missing the back drill files even though we think we are being told to use them.

Customer stackup is asymmetric we want stackups that are mirrored images from the center out. So in this case, they went three sheets of 1080 and three sheets of 2113, then 1080, 2113. We really want the two 1080s in the middle and the two 2113s on the outside so that there's symmetric or vice versa. Actual overall thickness of the customer proposed stack up can't be met in real life, we need a deviation request for that. Controlled impedances are specified on the fab drawing, but the customer took them out once they started routing the board. Those cause a lot of discrepancies because we have to look for all those on every layer, so if you start taking controlled impedances out that you are using for reference in your stackup, please take them out of your stackup impedance table before you give them to us.

Or there are times when we can't meet the controlled impences required in the customer stackup and we need to make adjustments, minimum plated through-hole wall to copper is less than eight mil, we talked about that and be careful of compliant pin manufacturers. Just like that reference design from the chip component manufacturer a lot of times the drill hole that they request that we drill, which is C is not large enough or is too large for us to meet the finish hole size which is B, so double check with your fabricator that the requirements are correct that we will actually achieve the correct drills hole size, which is the finish hole size circuit stubs that go nowhere, they have to be confirmed. And in this case, we found multiple stubs but the customer couldn't find them in their data so it was really tricky, and we had to compare notes side by side by WebEx.

Pad diameters are two small to meet class three annular ring. If you want class annual rings, you need to go by the drill bit diameter or you finish whole size diameter plus 13 or 15 mil instead of the plus eight or 10 mil. So that is part of your design, gang relief we talked about that, silk screen texts we see them on copper all the time, we cannot solder to silk screen texts. And another thing is symbols that go around devices that used to be used for hand soldering for enhanced assemblers to place center them those are no longer needed, and they really get in the way of other things like the height of your solder piece stencil in assembly and sometimes misregistration causes them to encroach too far over onto copper.

So if you don't need the legend and you don't need things, take them out of your design please. So that was my last one putting it all together to have the best design and preclude all these errors that we found plan with your fab assembly. From the top level down with your team of experts, you have access to a lot of FAEs at your material suppliers, your contract manufacturers, your fabricators work with these people for the best material utilization that stack up and utilize their assembly and fab guidelines in your designs before you even start your design. So you're not accidentally making wrong assumptions that turn out to be non manufacturable, avoid common design and documentation errors that we discuss and be glad for the concise documentation and the great design that you're providing for others. Thank you.
 

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Julie Ellis is a Field Applications Engineering Manager and Master IPC-A-600 Trainer for TTM Technologies, the world’s 5th largest printed circuit board fabricator. As a thirty-some year veteran in electronics and manufacturing, she’s seen a multitude of success stories and failures. Working on quality problems and failures cost significantly more time and resources for both manufacturers and customers than designing accurately in the first place. So Julie is committed to synthesizing her experience and expert resources into training and continuous improvement to anyone who will listen! The ultimate goal is assuring designs that reach factory floors have implemented as much forethought and optimization as possible in order to increase yields, reduce cost, and prevent failures.

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