¿Qué es el objetivo Z y por qué el suministro de energía es CA y no CC? - AltiumLive 2022

Heidi Barnes
|  Creado: February 3, 2022  |  Actualizado: August 25, 2022

¿Te has preguntado alguna vez qué ocurre cuando la corriente continua del diseño de fuentes de alimentación analógicas choca con las cargas digitales que funcionan con frecuencias de microondas? El aumento radical en la cantidad de desafíos en el suministro de energía ha provocado la aparición de un nuevo campo en la ingeniería dedicado exclusivamente a la integridad de la potencia. La integridad de la potencia tiene que ver con la insaciable demanda de procesamiento de la información, que exige complejos raíles de alimentación en el punto de carga para suministrar energía eficiente y de bajo ruido a las cargas de conmutación dinámicas.

Al mundo analógico le encanta apostar por el diseño de filtros con cuentas inductivas y amortiguadores, mientras que el nuevo mundo de la integridad de la potencia ha introducido el concepto de la impedancia objetivo. Esta presentación te sumergirá en el mundo de la utilización de la impedancia para suministrar potencia libre resonante a una carga. Por el camino, descubrirás por qué la impedancia plana es el mejor diseño, cómo medir la impedancia y cuál es el problema con los datos de los condensadores provistos por el proveedor.

Aspectos destacados de la ponencia:

  • Aspectos importantes sobre el nuevo campo de ingeniería dedicado a la integridad de la potencia.
  • Uso de la impedancia objetivo y cómo medir la impedancia
  • Por qué la impedancia plana es el objetivo de diseño
  • Llevar a cabo simulaciones para probar los diseños
  • Método Shunt Through

Recursos adicionales:

Transcripción (en inglés):

Heidi Barnes:

My pleasure to be here today at AltiumLive 2022 CONNECT. My name is Heidi Barnes and I am the power integrity product owner for Keysight Technologies, EDA simulation tools. And my presentation today is what is target impedance and why is power delivery AC not DC? If you look at this typical measurement of a power rail, this is what a power integrity engineer or power electronics engineer would do to look and see if their power rail is providing adequate quiet power to their load, to their design. And this is a picture of an oscilloscope screen. In blue is the current load, the dynamic current of the load in blue versus time turning on and off. And then in yellow is the resulting power rail ripple or noise that is seen in amplitude versus time. And what you see here is that the industry a lot of data sheets and most of the times will specify a specific maximum power rail ripple in response to a step load in current.

So, here you can see is a step load in current and the resulting ripple on the power rail. The response to a step load is the natural response. And this ripple that we're seeing here may be within spec. It may meet the min max ripple requirement and you could pass, but you notice that there is a ripple here, there is a resonance, and it's this resonance if we actually turn the current on and off at that frequency, we create what's called a forced response and this forced response is much larger than the natural response. It turns out that it's amplitude is roughly the amplitude of the natural times the Q or the sharpness of this resonance and this much larger forced response may actually fail your min max ripple requirement on your power rail. And what's causing this ringing? Well, there's inductance in the path between the voltage regulator of your power source and your load and that inductance times this dynamic load current will create a voltage drop or a voltage, what is it?

A voltage change and that is what's creating our ripple on the power rail every time we have this DIDT dynamic current. Now you might say that what's the probability of actually exciting that resonance but in the high speed digital world, we don't always have control over what frequencies will be excited in terms of there's the actual what we call mission mode switching of our digital trans receivers and digital logic. But we can also have a bursted data that has a much lower spectral content and even going in and out of power modes or turning devices completely on and off can create a very broad band, a wide band with dynamic spectral content that we have to design for and this is one of the challenges of designing power for high speed digital loads. The key takeaway here is that the forced response is worst case not the data sheet step load.

Now the next slide here is one of the reasons why I find power integrity not to be intuitive and this is, I actually have the board here. You can see this is the Xilinx ZCU104 evaluation kit and we have a FPGA mounted on the top and we also have the main power supply coming in here and the VCC into power regulator and on the back are a lot of our decoupling capacitors. And what you're seeing here with this 3D EM model is how the power comes from our regulator on the VCCINT power rail down through vias across layer 10 internal to the board and then back up to power the FPGA. And this VCCINT power rail can have upwards of 20 amps of current when it's complete. What is it? Running at maximum logic.

And what was interesting to me that it was very unintuitive I was sure we were getting set up to do this DesignCon paper to show how to power this device from a benchtop power supply and I was positive that if I ran this at 200 megahertz, so there's 400,000 flip flops that we can turn on and off with inside this FPGA. We set up sort of a test case of toggling these 400,000 flip flops. And I was sure that the highest frequency I could sort of toggle this at was 200 megahertz that I selected would have the worst case noise but it turned out that wasn't true. There was a lower, so 200 megahertz switching at 13, what is it? 200 megahertz switching on and off these 400,000 flip flops and if you looked at the total current being pulled from our benchtop supply, it was 13.5 amps.

So, a lot of current high frequency switching and if I looked at the power rail ripple, if I measured it, so we actually took measurements, I saw only 24 millivolts of peak to peak ripple, everything looked good. But when I did my EM analysis and actually looked at this did the simulations, I noticed that there was an impedance peak at 30 megahertz. And if I actually created a forced load, so I toggle these 400,000 flip flops on and off at 30 megahertz, even though the supply is only pulling 2.5 amps, it only requires 2.5 amps at this lower frequency, you'll notice that the dynamic ripple on the power rail is almost twice as large 47 millivolts. So, this was not intuitive. Lower frequency, less current draw, and high AC noise. And there you can actually download this paper from DesignCon 2020 and we go into details about the analysis that we did and we'll talk about that today too. We're going to be using this as our example. But the key takeaway here is dynamic current and voltage at the FPGA pins can help find worst case power rail noise.

Today's agenda is going to cover the power integrity basics. We're going to look at why flat impedance is the design goal. We're going to learn about designing in the impedance domain and the benefit that that can bring to get quiet power delivery to the load. With respect to designing with impedance and learning the importance of flat impedance, we also need to understand how do we measure microohms, how are power rail impedances in the microohms measured? And then finally we want to understand the importance of the models that we are going to be using and it is critical that we get accurate capacitor models and a lot of times the vendor models, they're good models but there may be the wrong model for what the simulation that we want to be trying to do. So, we're going to cover these three topics today and let's go ahead and jump into the first one, why flat impedance is the design goal?

Power integrity starts with target impedance and the Power Integrity Engineer uses this very simple and powerful equation to understand what's the target or what's the required impedance in order to keep the ripple on the power rail at a minimum. And it simply says that if I have a specification for the maximum ripple the component that I'm using will specify how much ripple or noise is allowed on the power rail and if I divide that Delta voltage by the Delta current, I will get a target impedance. Put another way is if I have a certain dynamic Delta change in my current times the impedance that I am seeing on that power rail, if I stay at the target impedance or below then I will not exceed my ripple voltage spec.

I like to take that simple concept and explore what it really means here. So, if I look at impedance versus frequency and look at how power is being delivered to meet that target impedance, we notice some interesting things. At low frequency all of the power is delivered by the power supply but my power supply cannot keep up as the frequency increases and it has a limited bandwidth. Above a certain frequency above the bandwidth of the VRM the impedance starts to increase and looks like an inductance. I can model the VRM as a simple series R-L low pass filter. Next, I can look at my decoupling capacitors. My decoupling capacitors can provide the higher frequency charge delivery as the power supply starts to increase in impedance, my decoupling capacitance on the boards starts to provide a lower impedance so I can meet my target impedance there but even a capacitor is not perfect and it has a limited bandwidth.

It has an ESL and there's a certain amount of inductance to get into the package. So, my printed circuit board decoupling has a limited amount of,  has a minimum amount of inductance that it can achieve. And then at very high frequencies, the package die will need to take over in terms of the power delivery and here you can see the internal capacitance, this decreasing slope here with the decreasing impedance with frequency is the capacitance inside the package and at high frequency that capacitor and the capacitance on die is providing the power delivery to the device. And this high pass behavior can be modeled as series R-C. If you put these three models together the series R-L for the VRM, the band pass series C-R-L for the decoupling capacitors, and the high pass R-C for the package die, we can do a very simple simulation here to show what happens when we put these three impedances and sources of power together in a schematic simulation.

And if we look at, we basically have a load here that we're sweeping in frequency from DC up to 300 megahertz to see what the response looks like. And we see that the VRM does a great job at the low frequency but the handoff, the transition from the VRM to the decoupling capacitors is not too good here. It's not really matched and we're getting a resonance. And then the same thing when we go from the printed circuit board decoupling capacitors to the package die we have another resonance here or a high impedance peak. It turns out that if we want to have meet that flat impedance target, if we want to avoid these resonant peaks here, we can select a capacitor the bulk capacitance on our printed circuit board decoupling should equal the inductance of the VRM so that increasing inductance of the VRM needs to be matched by a capacitor that's decreasing in impedance.

And that capacitance is simply the inductance of the VRM divided by the target impedance squared will give us the amount of capacitance we need. And then at the higher frequency, we have to look and see how many capacitors do we need to keep adding to get this inductance down on our decoupling capacitors and how low does that PCB PDN decoupling need to be. And there again, the impedance or that inductance in our PCB PDN we have to get that down to a point where it's equal to the package capacitance times our target squared or target impedance squared. If we meet these two equations, if we take our PDN decoupling capacitors and use the C that matches the VRM supply and the inductance that matches the package die, we can get this flat response that we see here down on the bottom right where impedance versus frequency, we've maintained a flat impedance in our power delivery network.

Why is this so important? If we look at the design where things are not matched I call this the Big V design, you may be selected an array of all the same type capacitors which drove this series resonant frequency ESR, impedance is very low but you have these resonant peaks here. So, this is a non flat multiple design and a Big V and then we have the example where we matched the capacitance with the VRM and the inductance with the package for our decoupling capacitors on our PDN and we have the flat design. We can take this impedance, each one of these designs here and excite it with two amps of dynamic current and we can look at what happens in the time domain. And very interesting here is this, basically in a CellScope type measurement, you can see the voltage ripple versus time and on the bottom here is the dynamic current that is exciting this ripple on the power rail.

And the dynamic load we start off at 178 kilohertz turning it on and off which is this first impedance peak here and the Big V design starts ringing in red. Then at the maximum of that first frequency we excite the second frequency at 12 megahertz and now we get what we call a rogue voltage wave. The resonance of the first one, first impedance peak is lining up with the resonance of the second impedance peak and we're getting a forced response that's creating a rogue wave.

Now, if you look at the flat impedance design, there are no impedance peaks and we're getting the response in green where things are critically and you only see the IR drop of the dynamic current there. Now we just saw how we can create rogue waves on the power delivery network if the impedances aren't flat. So, that kind of explains to us why it is so important to select the correct capacitors. And I'd like to make a quick comment about wideband gap gallium nitride technology that you're going to be starting to see more and more of in the power delivery world. And you can see a picture here on the left. This is the EPC eGaN device and how tiny it is here, but it's not just the size of the GaN switching devices here that's important.

If you actually look at this technology, the output in the active inductance, the inductance of that VRM, if you compare it to a MOSFET, the traditional MOSFET switches that are used in DC to DC converters, this graph here shows a measurement that Steve Sandler of Picotest did where if you look at the impedance of a traditional MOSFET switch it's the output inductance there of that switching regulator Is about one microhenry Whereas the GaN device is way down at 6.2 nanohenries. And what this means is you look at that equation that we're using for flat impedance, the inductance of the VRM divided by the target impedance squares, you'll see very quickly that we made this, what is it? 99.6% reduction in the inductance of the VRM so this inductance here is 99.6% reduced compared to the MOSFET which means we can significantly reduce the bulk capacitors that are needed in this power delivering network here using wideband gap devices.

And if you haven't seen it yet the power supply bricks are significantly decreasing inside for your computer and different devices out there when they use this type of wideband gap technology because not only is the device itself smaller but is switching at a higher frequency which means that it's output inductance is less and requires much fewer capacitors to achieve the power delivery. And so, the key point here is when selecting a voltage regulator for your design be sure to look at what the output impedance is or output inductance is because the lower the inductance of that regulator the less capacitance that you will be required to put on your printed circuit board power was your decoupling capacitors so this can save money and space.

Now let's take a little bit closer at what's the root cause of ringing on the power rail. It comes from a parallel inductance. It's basically inductance and a capacitance in parallel that can resonate and where is that coming from? Well, let's take a look at a very simple schematic here in the upper left and we can see that the inductance, if we model our VRM as an RL supply, that inductance of the VRM can resonate with our first bulk capacitor, but the bulk capacitor's ESL can then resonate with the parallel next smaller decoupling capacitor. And so, we have a couple of places where this ringing can happen.

And if we create just a very simple schematic to look at a single resonance between an inductor, a capacitor, and some real resistance in that resonating cavity there we'll find that we have our classic electrical equations for the frequency of the resonance but what's more important is what's controlling the peak heights? Because it's that impedance peak times the DIDT that's going to cause power rail noise and be the problem that we're trying to fight.

And so, if we look at the impedance peak it depends upon the Q, how sharp or how large is that Q and the Q of that resonance it depends upon the characteristics impedance of the L and C resonance and the real resistance that can dampen it out. A lot of times you'll see in a design they'll say to add a snubber resistor and basically we're snubbing that resonance by adding a more real resistance here to dampen it out. And this is also the real resistance in the ESR of your capacitors and the resistance of your power supply can help increase this real resistance and dampen in any resonances in the system. So, very good to remember that you may not want the lowest resistance in your power delivery network. If you try to design the lowest resistance possible you may find that any resonances in the system will actually increase rather than being improved.

So, we want to design for a flat matched impedance not the lowest impedance. Next, if you want to learn more about rogue waves and explore them a little bit further and learn about how they're created, Steve Sandler of Picotests who's an expert in the power electronics and power integrity industry has teamed up with Keysight to do a whole series of how to design for power integrity. And this was the first one, finding power delivery noise problems. This is a YouTube series and it goes into some detail on these, the different types of excitation that the load can do between the step responses and forced sine or square wave responses. But you can watch this video and there's actually a workspace that is available at the end for downloading. But what we're going to be looking at today is this Xilinx FPGA example.

And we've talked about the power supply and matching the impedance to the power supply but we also need to look at what is required by the load in looking at the delivery from our VRM across the printed circuit board and up into this FPGA and finally to the die. And now we're going to learn a little bit more as to why it's so critical even on the higher frequency side matching impedance to the load at a higher frequencies. The load can be described as one of the very useful things is to get a package die model of the load and if we can describe that package and die as an S-parameter model that we have an S-parameter block here that describes the behavior of that package and die. And if you get this type of package die model that's in S-parameter format like this, you can do something very practical.

And this is something that Jack Carrel at Xilinx came up with this analysis and it's very informative. At the die I can look at the impedance on the die side connection to this behavioral model and then on the printed circuit board, PDN side, I can connect three different test cases and open where I'm not connecting any power supply. To this package die I can connect a matched filled with five milliohm power delivery network to it or I can connect an ideal power supply that has no resistance in it and that would be a pure short. If I look at impedance versus frequency, the first thing I notice is that above 100 megahertz it does not matter what I do on the printed circuit board PDN. I can have a complete open or a short it doesn't matter. Above a 100 megahertz there is no impact from the PCB, a printed circuit board power delivery network.

But below that I find some interesting things. Obviously at DC there's a huge impact. That's where our power supply is delivering powers and our decoupling capacitors but there's this impedance peak here around 30 megahertz that is actually internal. So, with nothing connected this open case I see the internal 13 microfarad capacitor and I see that there's a resonance that's inside this package die. And that is the inductance getting from the package into the die, the inductance of the package ringing or resonating with the die capacitance and it's not something that I can eliminate but what you notice very quickly is that if I have some matched impedance, some real resistance in my power delivery network on the printed circuit board, I can help dampen the Q of that resonance.

So, this is just a very simple analysis but it gives us a lot of insight into what target impedance I want to be designing for my system and how high in frequency my decoupling capacitors need to go. One other thing to look at is that if I look at that PI ecosystem of the FBA package die my printed circuit board PDN power delivery network and the VRM and decoupling capacitors, if I look at that whole system and try to connect them together, I really want to look at what is the performance of that. And so, in measurement world I find there's impedance versus frequency I can measure at the VRM but that may not be the same performance that the FPGA is seeing. And so, if I try to measure at the FPGA I would expect it to be similar or even lower impedance at the FPGA near all of the small decoupling capacitors.

But when I try to measure at the FPGA I run into problems. I'm having to measure through a very small via to get to the power plane. And so, that small via that I'm trying to measure through actually has a fairly high inductance. And so, that's actually creating some problems to try to measure what is happening. So, that is where simulation comes to the rescue. Simulation actually can take an accurate model of the printed circuit board PCB power delivery network with all of the decoupling capacitors and we can attach our model of the VRM, we can attach the package die model and now we can actually see what the whole system is doing even at the higher frequencies.

And you can see here the simulation can also parallel all of our IOPS on the package together to look at what that combined reduction and inductance is and then we can actually look at what the impedance the die sees, and that's where we actually discover this 30 megahertz resonance. In measurement we didn't really see it. We weren't able to get our fixturing low enough in impedance to actually see that resonance there but in simulation it was very obvious.

So, if you want to explore this real world test case we actually have the power integrity workflow in three easy steps on YouTube and it uses the Xilinx ZCU104 evaluation kit as the example and this is the basis for the analysis that I just showed you with the impedance versus frequency of the whole PI ecosystem that showed us the resonance at 30 megahertz. And the way this three step process works is we bring in the board, we run our analysis, we do a DC, oh I'm sorry, we do a DC analysis first and I always start with DC because that makes sure that the board imports correctly and we verify that we have the correct voltages being delivered to the load. Then this DC analysis can be copied to an AC analysis with the decoupling capacitors.

We can make sure that we have accurate models for the capacitors, we can optimize the capacitors, we can analyze that impedance and verify that we're meeting the target that we desire. And then we can export that PCB PDN, and EM model to a schematic and we can then connect it to our VRM packet die model and also create a dynamic load for it. And here you can see we created a dynamic load that we can change it to 30 megahertz or 200 megahertz. And it's that simulation once we realized that there was an impedance peak in our simulation day data and went ahead and excited it in the time domain. So, we took our power integrity ecosystem schematic and we ran it with a 30 megahertz load and we were able to simulate this dynamic ripple.

And then once we increased the switching frequency of the dynamic load to 200 megahertz we actually simulated the reduction in dynamic ripple with the higher switching frequency here running those 400,000 flip flops. So, what was very exciting is this matched, our simulation here matched with the measurement that I showed you at the beginning of this presentation. So, at 30 megahertz with lower current we actually have more ripple because of that impedance peak than we do at the high frequency, with more dynamic current. And this type of simulation it's setting up, running your power delivery network analysis in simulation and designing for flat impedance. This is another very useful thing that you can do. You can run a Monte Carloto simulation to look at how robust your design is, how sensitive is your design to component tolerances.

And just doing comparison on that simple schematic that we started with you can see that the flat impedance design is much less sensitive than the Big V design. The flat impedance design here is not making a this is a log scale on the left. So, the Big V design is a much larger variation here than the flat impedance design and just another reason for doing matched impedances in power delivery. So, in summary the parallel L and C resonance in its, what's it? The parallel L and C resonate in the time domain but it's much easier to find this resonance and eliminate it and flatten this out in the frequency domain. So, if you're looking for worse case power rail ripple, it's much easier to find the problem in the frequency domain where those impedance peaks are and look at how to reduce them.

And I think in terms of designing for flat impedance you want to select the bulk capacitors so that you balance the inductance of the VRM divided by target impedance squared and the printed circuit board power delivery network, the inductance needs to be brought down so it's low enough such that that inductance equals the package capacitance times the target impedance square. So, basically that helps define the circuit board decoupling, what is it? Behavior there, the min and the max frequency of power delivery.

So, the second thing is to go in how are power rail impedances in the microohms measured. And one of the things that's interesting is why do we need measurements and what do they show us about the real world. And measurements actually help us verify the fidelity of our simulation tools and make us understand what sort of accuracy we do need with our simulation tools. And here's a simple board with five parallel capacitors. We can import that design into a layout tool and then we can create our 3D model for EM simulation. And what's interesting is five capacitors in parallel and with a SPICE simulation, you would expect five times the capacitance, five times less ESR, and a five times less inductance. But in the real world when you actually measure it, you find that the inductance is not reduced that far, that there's a lot of parasitics inductances and path parasitics in the printed circuit board.

And so, our measurement does not match with a simple five parallel capacitors as SPICE simulation would do. And another one that's even more interesting is if we take those five parallel capacitors and have different values, so say a large capacitor on the left and a small capacitor on the right, we find that in SPICE again, SPICE doesn't pick up the parasitics of the printed circuit board in a lump simulation. And so, the impedance will look the same no matter where we measure it. And that's the black curve here impedance versus frequency. But in actuality if I measure at the VRM on the left with the larger capacitor I have the red trace here, which is very different than if I measure next to the small capacitors where I see a lot more of the interaction of the small capacitors with each other so it does matter where you measure, and if you want to get the same fidelity, if you want to get correlation between simulation and measurement you're going to need to include the printed circuit board EM model and not just do simple lump SPICE simulations.

Now, in order to measure low impedance there has been some past presentations by Keysight from our instrument division using network analyzer and this shunt through method with a vector network analyzer. The shunt through method is, it takes a little bit to understand but you basically do an S-parameter measurement, a 2.S parameter measurement which is this S21 data, the signal that is at port two from port one and you have this simple equation here that converts that S21 measurement to an impedance when you're measuring the device under test in a shunt to ground sort of set up. And of Steve Sandler of Picotest teamed up with Benjamin Dannan to create this application note.

Picotest actually makes a probe where port one and port two are connected together at the probe tip and basically makes it very easy to do this 2-port shunt sort of connection to your printed circuit board PDN and take that measurement. And there's also a presentation on how this works but I like to emphasize that when you take a measurement you can also set that measurement up in the simulation world and just explore how it works. And so, when measuring impedance versus frequency of the network analyzer most of us think of it as a one port measurement. So, you have your impedance of your network analyzer, 50 ohms and you connect that up to a device under test and the one port that reflection will tell you what the impedance is.

But the problem is a network analyzer has a limited dynamic range, and the 50 ohms of the network analyzer going into milliohm device creates a very large reflection and the sensitivity struggles. And so, that's what this plot here is showing is that the one port is in blue we can get down to milliohms and microohms and impedance, I'm sorry. I backed up here. In measurement in red the network analyzer does not have the dynamic range with the one port measurement here. And so, you're seeing its trouble getting down to the low frequencies but this shunt configuration, let this get down much lower and the way the shunt connection works is that instead of, in series with between port one and port two the impedance that we want to test is actually taking the signal line that goes from port one to port two and we're shorting it through that very low impedance to the ground connection.

Now, the way this measurement works you'll notice that in order to do the measurement we have to be careful that there's no ground currents. The network analyzer assumes that port one and port two have the same ground potential. And so, we actually oftentimes have to put a common mode rejection transformer in here to prevent currents on the ground rail from corrupting our measurement. So, if we look at how that is done a little bit closer, you can see here's our device under test and it has a capacitor from port one to port two and along that signal line we're taking our device under test of the low impedance capacitor we want to measure and we're shorting it to go around there with that connection. We can also look at this setup here for this measurement of this low impedance resistor and notice that any series resistance that increases the port resistance of the network analyzer in port one and port two can actually help change our dynamic range. So, this is another trick. If you're measuring a capacitor you want basically the 50 ohm connection to get down to very low impedances.

But if you're are measuring an inductor you might want to actually capture the transition from the inductance to the capacitance as well as grab the low RDS of, what is it? I'm sorry the inductor's resistance and in order to do that you can add some series resistance to each port to change the dynamic range of the network analyzer. So, there's some tricks here to getting these measurements to work. And one last thing I wanted to comment on is how you do the calibrations may also influence what can set up an equation to use for getting that impedance. Again, this one is very interesting. If I do a full 2-port network analyzer calibration so that I have S_21 and the S_11 and S_22 terms I can start with if I just look at my network analyzer may measurement port one and port two and look at the impedances of that black box what's interesting is on the network analyzer for this measurement I commented that port one and port two ground are the same.

And so, I can redraw that as a Delta configuration and then I can convert the Delta impedances to a T network classic circuit theory. And then if I look at this T network and say, "This is the black box that I'm measuring this shunt configuration of this capacitor," I notice that the shunt impedance that I want to measure is equal to Z21. So, this component here that's shunt to ground is exactly what I'm trying to measure that impedance shunted to ground and then I can use the transformation of S-parameters to Z parameters to get the Z21. Now this conversion, if I use this for 2-port calibration and use the Z21 method here to get this shunt impedance I'm much less sensitive to the fixturing or any series impedances in connecting to that shunt impedance.

But on the other hand, it does require a full two part calibration to do that. Now the other thing, one of the reasons why do we want to measure microohms and milliohms, why do we care about measuring these very small impedances is because in order to design these power rails for low voltage high current devices, the actual target impedance is getting down into the milliohms. And also when connecting these capacitor models to an EM model of our printed circuit board, we want to make sure that we're not double counting the mounting inductance because our EM model is going to simulate this mounting inductance. And you can see here, this is a little printed circuit board where I've shorted the pads across there, short of the pads together and if I measure that I'm basically looking at what's the mounting inductance of this fixture.

And you can look on the graph here is the resistance of this mounting fixture at low frequency and then the inductance of it as we go up in frequency. And so, the mounting conductance can be modeled as an R in series with an L. This 2-port shunt impedance technique, a lot of times if I'm trying to measure a point on actual application board, this is one technique that I've used before where I solder two coaxial cables together. One goes to port one goes to port 2 and the signal pins are soldered together. Before I attach those two cables to the application board I can run a simple response through calibration and calibrate my network analyzer and then solder to my board and take the measurement. And if I do that simple through calibration, then this equation here is one that I want to use with the simple, just a S21 through calibration.

So, in summary here on taking measurements why are we so interested in being able to measure these very small parasitics? Is because we really want to get our simulation and measurement correlation driving that together. SPICE models don't always capture all those PCB parasitics and if we want to simulate them we also need to verify that we have those models correct that we're being using. So, impedance measurements in the milliohm range are needed to create accurate component models to validate the EM simulation models and debug PDN noise. And the 2-port shunt method is the one that we want to use and that's the shunting pins is equal to 50 ohm ports divided by two 25 times S21 divided by one minus S21.

And finally let's go ahead and we'll conclude here with the importance of really good models for our capacitors, for the capacitors that we're using in the design of our power delivery network and why the vendor data may not be what you think it is. Now remember and we've been showing you we can model a capacitor as a series R-L-C and the biggest thing here is that capacitors are not just capacitors. They have a series inductance and a series resistance. And at that resonant frequency is where we see the ESR and below the resonant frequency it looks like a capacitor with decreasing impedance versus frequency and above that self resonant frequency, it starts to dominate by the inductance and it looks like an inductor with increasing impedance.

If we look at how we design for flat impedance, I can walk you through a very simple example here of impedance versus frequency and on this graph we have in black, the simple model for our VRM. It's an R-L model. Like we discussed before once we reach the limit of the bandwidth of the VRM that active inductance starts to increase the impedance and the VM cannot keep up. To design for flat impedance I take that 15 nanohenries of active inductance and divide it by the target in pence squared of 24 milliohms and I find that I need a 16.4 microfarad capacitor. So, if I combine the red downward slope performance of the capacitor with this upward one of the inductors from the VRM I get the blue trace. Now the decoupling capacitor I selected this big 16.4 microfarad capacitor doesn't go forever.

It has an ESL of 875 picohenries so then I take that same inductance divide it by the target impedance squared of 24 and I find that I need a capacitor of 1.5 microfarads. Well, the good news is, the 1.5 microfarad capacitor I need is in a smaller package and I can find one with less inductance so this smaller capacitor with less inductance can go a little bit higher in frequency and that's the green trace here. So, by adding this, the 1.5 microfarad capacitor, I now can get out to a little bit higher frequency but that capacitor also has some inductance into it. But this whole design you'll notice that the critical parameter is what is the inductance and then that determines my capacitance. And so, it's very important that I have an accurate measurement of the inductance.

And if I look at where the inductance comes for that capacitor, there's inductance internal to the capacitor, but there's also mounting inductance. So, how I can mount that capacitor to the print circuit board will also influence the inductance. And here you can see there's these two boards. One is and actually I can show it here. One is 63 mils thick and the other is only eight mils thick. Each one has a capacitor with one ground via and then a capacitor with 12 ground vias, so a little bit of island here with 12 ground vias. And the idea here is I've got a 63 mil thick board, and I want to know how can I improve or reduce the inductance of my capacitor? And it turns out if I add 12 ground vias there, I can influence that inductance. I can bring it down from 620 picohenries to 450 picohenries.

So, adding the additional ground vias as we would expect reduces the inductance, the mounting inductance. But I notice that there's a much bigger impact if I make sure that I keep the dielectric layers thin between the power and ground layers. And here even with one ground via, it's better than 12 ground vias of the thicker dialectic case. So, the main point here is the mounting inductance does have a big influence on the mounting. Topology can have a big influence on the inductance in your decoupling capacitors and I highly recommend that you look at trying to get a thin dielectric between your power and ground layer. And eight mills is very easy to fabricate. Even two or three mills is still within the fabrication capability of most design houses. So, definitely an easy thing to achieve in your stackup.

And then the next thing is, why am I so concerned about understanding this mounting inductance and we saw that how we design that footprint in the stackup of our board, different things can influence that mounting inductance. My EM simulator is actually simulating those different topologies for the mounting inductance. And so, when I connect my capacitor model to my printed circuit board, EM model, I want to have a capacitor model with the mounting inductance removed. But if I'm simulating with SPICE, if I don't have an EM model of my printed circuit board, then I want to include the mount. So, I really need two different models. One model, if I'm just doing a simple SPICE simulation, and I want to have the mounting inductance included or a capacitor model with the mounting inductance removed so that I can connect it to my high fidelity PCB EM model.

Now, I do have some slides here. I probably won't go into as much detail, but one of the things I do like to do is take a measurement of a capacity. You can see that in red here. And then I like to create a model, a lumped element model in my simulation environment, because then I can take and explore component tolerances. I can vary the different values and look at the behavior of my power integrity ecosystem based upon some minor changes to my component behavior. If I just have an S-parameter model, it's much harder to work with that if I want to vary anything, but you can see here, this capacitor doesn't actually match a very simple R-L-C model. If I used an R-L-C model of this capacitor, I would get a little, I would be off on the inductance.

So, what do I do? Well, I can come up with a, say for ceramic capacitor two parallel capacitors, and I can come up with these two parallel capacitors and look at those values and tune them. And it turns out I can actually then get a very good fit with my measured S-parameter data. So, here you can see I run, do some tuning or run an optimizer, and I can tune these two parallel capacitors to have a very good fit with my measurement. And now I have a model of my capacitor that allows me a lot more flexibility in looking at tolerances and different things. This is an example for a tantalum capacitor, and it's even further from an ideal R-L-C type of capacitor behavior. It has some extra sort of break points or frequency behavior here.

And again, Steve Sandler of Picotest helped come up with this representation of the tantalum capacitor and what's the behavior that it has. And again, we can run an optimizer to optimize, to match with measurement. And you'll notice that this model actually has the mounting inductance in it and we can take pick a direct measure of that mounting inductance by shorting the pads together here and populate this R-L inductance. And what that means is by shorting those pads together and getting this R-L term, we can put that directly into our model and optimize all of the other parameters and then we end up with a model that matches with measurement. And now we have this model here matches with measurement, but I can turn the mounting inductance on and off. So, I can short this mounting inductance, pull it out for if I want to connect to an EM model of the printed circuit board, or I can leave it in if I want to just do a simple SPICE simulation of the network.

So, that's a very powerful method here. You can also take a measurement of the capacitor and just simply do a S-parameter of that mounting inductance. But I'd like to show here again, this is just a little more detail on if you have a capacitor model and you tune the different parameters and include that mounting inductance in the bottom, then you can get a model that makes it easy to turn that mounting inductance on or off depending on how you're going to be doing it using in simulation. And if you look at down on the bottom here, these are three capacitors that were used on the Xilinx ZCU104 evaluation kit. And you'll notice that the larger capacitor here matched pretty well between my measurement and the vendor model but when I removed the mounting inductance, it showed me that the vendor model still included some of the mounting inductance.

As I got to some of the smaller capacitor, the differences got a lot larger for those smaller inductances. And here you can see the 68 microfarad capacitor, once I remove the mounting inductance it was significantly different than what the vendor was providing. So, the vendor is definitely providing some mounting inductance in their data. And if you want to have a model for connecting to your printed circuit board, PDN EM model, then you're definitely going to need to do some measurements and create your own models for simulation. Now, let's see. If we look at the accuracy, the same sort of thing has to be done for the printed circuit board EM model. We just verified our capacitor models and took a look at what we were using there. But we also have to make sure that the EM model we have of the printed circuit board makes sense, and that we haven't made any errors in our material descriptions and stack ups and one of the ways to do that is to actually measure a bare board.

And so, that was one of the things we did with the Xilinx ZCU104 evaluation kit is we actually measured a bare board. We took off all the components so there's no capacitors on our power delivery network. And we simply measured both at the VRM. We measured it a few locations and compared that with simulation. And down here on the left, you can see that there's also a challenge when measuring. You can measure the same side, port one to port two connecting to your power rail at the same location on the same side of the board, or you can measure at the top of the via with port one and the bottom of the via on port two and connect internally with that via to your power rail and that's the blue trace here.

So, at low frequencies, we get very good agreement between those two types of probing techniques, but at higher frequency we start to see some variations there. So, the long story short here is basically I use this bare board measurement to really focus in on what's the capacitance that I'm seeing on this bare board measurement and does that match with my simulation? And then if not, then I can look at my stack up topology and my dielectric constants and see if there needs to be some adjustments. At the higher frequencies, you can sort of look for some of the resonances, but again, sometimes the measurement techniques can make it difficult to get exact correlation with the simulation at the higher frequencies depending on the calibrations. So, that 2-port shunt impedance method is also useful there for measuring the bare board.

And one last comment on the capacitor vendor data here, this was a paper that was done or presentation that was done by Ben Dannan and Steve Sandler, myself for EDICION this past year. And Steve Sandler basically said, "Well, let's measure three identical, or not necessarily identical, three 0805 capacitors. They all are in the same package. They're all one microfarad capacitors, but let's see how they compare." And the vendor data said that the inductance was 709 picohenries for this AVX capacitor. The were lower at around 400 picohenries of inductance. And if you looked at this vendor data, you would say, "Oh, I want to select the lowest inductance component." And it turns out that if you actually measure these devices and go look at what the mounting inductance is and remove that fixturing and mounting inductance from the measurement of the capacitor, that you actually end up for all three of these capacitors, they're all 0805 packages.

They end up with very similar inductance between 140 to 170. And what's eyeopening is that the AVX capacitor actually had the lowest internal capacitor inductance whereas the major data from the vendor actually said it was the worst one. So again, just emphasizing that the vendor data is not always going to be the data that you want to use when connecting to high fidelity PCB EM model. And just to emphasize this one last time, people will oftentimes say, "Hey, this looks great. You were able to measure the actual capacitor, compare it with the vendor data and then you created a better model or de-embedded that mounting inductance." But what happens if I don't have that measured data? What happens if I can't do it, or I'm crunched for time and, or I'm early in a design and I really don't have access yet to take those measurements?

Well, first of all, I would say, as a power integrity engineer, you really do need to learn that skill. You need to be able to measure what you are buying and verify that you're really getting the performance that you think you're getting from those capacitors. You also need to be able to verify that your design is working the way you expect. So, being able to do these 2-port shunt impedance measurements is a very valuable skill to have. But if you can't get to that measurement, you'll notice here that the capacitance is very accurate with the vendor model and so you can use that C value. The ESR has a little bit more variation, but you can use that vendor. The resistance at the self resident frequency there, that resistance can be your ESR. And I would just use a series capacitor and series with a resistance as the model for the capacitor and set the ESL to zero.

So, if you don't have measure data, I usually leave the ESL equal to zero, and I don't use the vendor model. So I use the C, the ESR and set the ESL to zero. What that does in my simulation is provide me with a best case scenario and then I can always add some ESL back into my model to see what it does to my power integrity ecosystem simulation but it would be much worse to double count that inductance and just use the vendor model without looking at that. So, just a suggestion there. And the whole reason back to our plot here of the ZCU104 evaluation kit, the VCC and power rail, by verifying the accuracy of our capacitor models, by verifying the accuracy of our bare printed circuit board, compared to the bare board simulation and validating our simulator, putting that all together, we were able to identify that 30 megahertz peak at resonance in the system, and then create this simulation methodology here of checking things out with DC, creating our AC EM model of the printed circuit board PDN, and then exciting it in the time domain.

And being able to show that the both measured and simulated data showed much less or showed a lot more power rail ripple at 30 megahertz with only 2.5 amps versus 200 megahertz with 13.5 amps. And this simulation is actually really powerful because not only does it show us the voltage on the power rail here, the FPGA voltage in gold on the power rail, the simulation also lets us look at the FPGA dynamic current which is something that is not realistic to do in measurement, but in simulation, we can see how large the dynamic current is at 30 megahertz versus the blue dynamic current at 200 megahertz. So, the power rail ripple variation between 30 megahertz and 200 megahertz is maybe 50% greater for the 30 megahertz.

But the dynamic current is almost more like a factor of 10 larger. So, a lot more going on here with the dynamic current as we get close to that resonance. So again, power integrity is not intuitive, simulation with measurement enables predictive models for design optimization and troubleshooting. And finally, in summary, I just can't emphasize enough how flat impedance is the PI ecosystem design goal for resonant free power delivery. It's very important to learn how to make 2-port shut impedance measurements to get good models, verify simulations and debug noise problems and be aware of vendor capacitor models. Avoid double counting the mounting inductance when using with EM models of the printed circuit board. And then finally, give it a try with the 3-Step DC, AC, Transient PathWave ADS: Power Integrity Workflow with PIPro the YouTube video that I was showing you there that has the downloadable workspace.

And I have a little bit of a history lesson. Just a real quick thing to leave you with something to think about, if you remember the Transatlantic cable story back in 1858. The first time they strung the cable across the Atlantic, it didn't work. And the solution at that time was in 1858, the signal quality declined rapidly slowing transmission to an almost unusable speed. The cable was destroyed the following month when Wildman Whitehouse now infamous, applied excessive voltage to it while trying to achieve faster operation. So, basically because the signal wasn't, they couldn't hear, it was becoming unusable, they just started cranking up the power, the voltage hoping it would work better and it failed. They didn't have a Signal Integrity Engineer back then. And so, I am asking the same thing about Power Integrity Engineers. If you're a Power Integrity Engineer, are your designs still leveraging decade capacitor values?

Are poor designs band-aided with added filters in more capacitors? So, where is the Power Integrity Engineer? Instead of just throwing more capacitors on a board to try to fix a problem, where is the Power Integrity Engineer to design it from the beginning for optimum quiet power delivery? And if you are new to power integrity, there's the how to design for power integrity, five part series on YouTube, and that one's by Steve Sandler of Picotest. And then what is it? Steve Sandler is often saying that pathway of ADS is this simulation environment is the only one out there that can do the end to end power integrity ecosystem looking at both in the frequency domain and the time domain and including high fidelity models of the different components. So, with that, I would definitely like to acknowledge my co-collaborators Steve Sandler of Picotest and Jack Carrel of Xilinx. And you can see, I have referenced here one of the key papers that was part of this presentation, and we have some links to Picotest, to Xilinx and then also to the YouTube videos that I've been mentioning in the presentation today.

So, with that, thank you very much for attending this tutorial. And now we'll move on to Q&A.

Sobre el autor / Sobre la autora

Sobre el autor / Sobre la autora

Heidi is a senior application engineer in signal and power integrity. Her recent activities include the application of electromagnetic, frequency, transient, and channel simulators to solve signal integrity (SI) and power integrity (PI) challenges. Heidi’s experience includes six years in SI and PI for ATE test fixtures for Verigy, an Advantest Group, six years in RF/Microwave microcircuit packaging for Agilent Technologies, and ten years with NASA in the aerospace industry. She was awarded the 2017 DesignCon Engineer of the Year Award.

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