If you joined us for the May 10th, 2018, PDN Analyzer™ webinar then the following will be a recap, if not here’s what you missed. You can also view the presentation slides and recording.
Power Delivery Network () Design Issues
A low supply voltage at your loads can cause issues like processors outputting faulty logic. These things happen when there is an unexpected voltage drop.
If your current is too high it creates too much heat in the copper delaminating the board and/or separating vias. With via(s) destroyed so is the functionality of the board.
Copper island and peninsulas can be a cause for concern as they can resonate with with other signals on and even outside of your board. Troubleshooting these is very difficult, its best to find and fix these issues before they occur.
Q: What determines PASS/FAIL conditions?
A: PASS/FAIL conditions are determined by the user and can be set for each source or load.
Q: Is there any plan to add temperature estimation?
A: This is something we know that people want and we are currently looking into how to best implement this.
Q: Are there any plans to implement AC analysis?
A: Yes, we plan to continue improve which includes adding AC analysis.
Q: Can you reverse the color scale?
A: Not at this point but we are currently working on this functionality.
Q: Can loads in multi-channel instances be added in batch?
A: Yes. But remember when you load different network configurations in batch mode each configuration will be simulated individually from each other.
Q: Can you change copper weight?
A: Not at this point. But you can change how the conductivity and resistivity of the metal is defined.
Q: Does it handle blind vias?
A: Yes, can handle blind, buried and standard vias.
Q: Does PDNA simulate with multiboard?
A: Currently it does not, you would need to analyze each board individually.
Q: Can PDNA provide inductance of the power path?
A: No. Reactive attributes of the copper structures are not calculated because PDNA currently focuses on DC.
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