The software includes a number of validation checks, which can be included as an output, during output generation. Each produces an HTML report file. Validation outputs can be added to the active Output Job file from the menu of the [Add New Validation Output] control in the Validation Outputs region of the file or from the Edit » Add Validation Outputs sub-menus of the main menus. Note that the…

Parent page: Design Rule Check (DRC) The software supports the ability to selectively waive any DRC violation. This allows you to effectively 'suppress' a violation that is considered not to be an issue without having to craft a special (and maybe complex) design rule to facilitate the design situation. Waiving a DRC Violation DRC violations can be waived by: Selecting the required violation(s)…

Parent page: Design Rule Check (DRC) With care and attention and staged design rule checking along the way, running that final Batch DRC on the finished, fully routed board may yield only a few design violations, if any. However, there may be a sizable quantity of violations flagged, and now the task becomes one of resolving those violations. DRC reports generated by running a Batch DRC can…

Parent page: Design Rule Check (DRC) Configuring the DRC Configuration for design rule checking is performed in the Design Rule Checker dialog accessed through the Tools » Design Rule Check command from a PCB document. The Design Rule Checker dialog showing defaults with certain Online DRC checks disabled to improve PCB Editor performance. Use the associated options to include a design rule type…

Design Rule Checking (DRC) is a powerful automated feature that checks both the logical and physical integrity of a design. Checks are made against any, or all enabled Design Rules, and can be made online - in real-time as you design - or as a batch process, with results listed in Altium Designer's Messages panel and a (optional) generated report. This feature should be used on every routed board…

The design rules of the Signal Integrity category are described below. The Signal Integrity category of design rules. Signal Stimulus Default Rule: not required This rule specifies the characteristics of the stimulus signal used when performing a signal integrity analysis on the design. This is the signal that is injected at each output pin on the net under test. The worst-case result is returned…

The design rules of the Placement category are described below. The Placement category of design rules. Room Definition Default Rule: not required This rule can be used in the following ways: To specify a rectangular or polygonal region on the top side or the bottom side of the board, where components are either allowed in, or not allowed in. To define a named region (area) on the board, where…

The design rules of the High Speed category are described below. The High Speed category of design rules. Parallel Segment Default Rule: not required This rule specifies the distance two track segments can run in parallel, for a given separation. This rule incorporates a Layer Checking option as a constraint. Because of this, it is not possible to define a layer-based rule scope, for example to…

The design rules of the Manufacturing category are described below. The Manufacturing category of design rules. Minimum Annular Ring Default Rule: not required This rule specifies the minimum annular ring required for a pad or via. The annular ring is measured radially, from the edge of the pad/via hole to the edge of the pad/via (also referred to as the land perimeter). For very dense designs,…

The design rules of the Testpoint category are described below. The Testpoint category of design rules. Fabrication and Assembly Testpoint Style Default Rule: required i The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in…