Flat Panel Display (FPD) link is a protocol for transmitting digital video streams from graphics processors to digital displays. It is an internal interface and uses low-voltage differential signaling to transmit pairs of serialized video bits. It does this by serializing parallel TTL data from graphics cards. Using three pairs of data and one pair for clock, the protocol transmits 18-bit RGB video. Newer FPD links use four pairs of data and one clock pair to transmit 24-bit and 30-bit color.
Previous to Flat Panel Display link, video streams were transmitted in parallel fashion along 21 wires. The wires took up much more real estate in graphic chipset pinouts, in traces along printed circuit boards, and in interface cabling to display devices. Serializing parallel bit streams reduced pins and traces necessary to transmit. Developing flat panel display using low-voltage differential signaling improved production costs by implementing video streaming using fewer wires.
Subsequent Flat Panel Display link versions have further improved video stream transmission. Improvements brought integrated clock and data, reducing four pairs to one. One signal pair further refined cable wiring to remove wired pairs. Needing only one pair to transmit 24-bit RGB video streams allowed cables to be installed into smaller spaces. Use of one pair also eliminated errors due to skew, leaving clean transmission across longer cables.
Flat Panel Display link protocol came about when video graphics array data was in need of efficient transmission. Graphics processors output color and control bits in either 21 or 28 parallel words for delivery to offboard displays within computer systems. This motivated chip designers to come up with an elegant means of sending data across cables.
A parallel-to-serial scheme came about early in the 1990s when low-voltage differential pairs came on the design scene. Able to transmit large amounts of data at high speed was necessary to get video streams from graphics card to displays. LVDS allowed transmission along low-power with equal and opposite signal pairs able to cancel common-mode noise.
Flat Panel Display link is the established protocol for sending display information. The protocol continues to see wide use in many digital systems from home entertainment to automotive markets. The latest version FPD III recognizes mating protocols such as HDMI, I2C, and SPI making it versatile for use with a variety of video streaming applications.
There are two serial stream options for transmitting video streams with FPD. Older versions transmit 21 bits of data across three LVDS pairs while later versions transmit 28 bits of data across four LVDS pairs. Transmit speeds reach 227 MHz after serializing into pairs that are seven bits deep.
Several parts are highlighted, below, for your consideration.
This part is designed to work with Flat Panel Link II protocol to minimize video stream transmission to one low-voltage differential pair. By reducing transmission to one pair, both printed circuit board and cabling real estate is preserved. With minimal use of space, both cost and weight are reduced making it an elegant choice for use in automotive or other small devices needing high function for video streaming.
The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and VLDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.
Found on page 2 of DS99R421 datasheet
This part is designed for use with Flat Panel Link III protocol to deserialize bit streams. This interface is full duplex and includes communication with I2C and SPI. The part automatically senses the FPD-Link II channels and supplies clock alignment and de-skew functionality. There is an evaluation module, the DS90UB948-Q1, to use for developing within systems.
The DS90UB948-Q1 s a FPD-Link III deserializer which, in conjunction with the DS90UB949A/949/947-Q1 serializers, converts 1-lane or 2-land FPD-Link III streams into a FPD-Link (OpenLDI) interface. The Deserializer is capable of operating over cost-effective 50Ω single-ended coaxial or 100Ω differential shielded twisted-pair cables. It recovers the data from one or two FPD-Link III serial streams and translates it into dual pixel FPD-Link (8 LVDS data lanes + clock) supporting video resolutions up to 2K (2048x1080) with 24-bit color depth. This provides a bridge between HDMI enabled sources such as GPUs to connect to existing LVDS displays or application processors.
Found on page 1 of DS90UB948-Q1 datasheet
This part is suited for use with both Flat Panel and Flat Panel Link II transmission schemes. It boasts high throughput at up to 2.38 Gbps and is compatible with LVDS TIA/EIA-644 specification.
The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL (LVTTL) data into four serial Low Voltage Differential Signaling (LVDS) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28-bits of input LVTTL data are sampled and transmitted.
Found on page 2 of FIN3385 / FIN3386 datasheet
Working with graphics processors typically require a good FPD link serial/deserializer IC. FPD link ICs convert parallel data streams into serialized bits for transmission as LVDS pairs. Transmitting video streams in LVDS pairs maintains signal integrity during high-speed transfers across long cables. The website has links to vendors parts, along with a parts selector engine to assist your search.
Stay up-to-date with our latest articles by signing up for our newsletter.