Your MCU Got Smarter. Your Supply Chain Got Harder.

You're selecting a microcontroller (MCU) for a product shipping in 2027. The part you had in mind now comes with a neural accelerator, whether you specified one or not, at a price that's hard to refuse. Then the distributor's quote comes back showing availability months away.

You're now looking at an MCU with a neural processing unit (NPU) you didn't ask for and a longer lead time. AI demand is behind both, but it's creating pressure in different parts of the semiconductor supply chain. Accelerators are moving into embedded processors, while AI infrastructure is consuming select mature-node capacity that's also used to build power-management ICs (PMICs) and power discretes. You have to manage both in the same design cycle.

If you're specifying MCUs for 2027 builds, five trends deserve your attention.

Key Takeaways

• NPU-equipped MCUs are now shipping from TI, ST, NXP, Renesas, and Infineon, and TI’s launch pricing shows that on-chip inference has reached the sub-$1 MCU tier. 
• Many endpoint-AI workloads concentrate computation into short bursts, often on sub-1 V core rails, making transient response, regulator selection, and decoupling central to the design.
• AI demand is tightening the supply of select mature-node capacity used by power management, analog, and embedded components, extending lead times and pushing prices upward.
• Channel reports indicate that some distributors are already asking customers for full-year 2027 requirements.

1. NPU-Equipped MCUs Go Mainstream

The turning point came at Embedded World in March 2026, when TI said it would integrate its TinyEngine NPU across its entire microcontroller portfolio. The anchor component is the MSPM0G5187, an 80 MHz Cortex-M0+ with an on-chip NPU, now in production. TI launched it at under $1 in 1,000-unit quantities, though distributor pricing was around $1.60 in September. TI rates the accelerator at 2.56 GOPS, with up to 90 times lower latency and more than 120 times lower energy per inference than a comparable MCU without an NPU. At that price, local inference is a viable option for designs that previously sent data elsewhere for processing.

Arm CPU Cores Are the Common Foundation

Across TI, ST, NXP, Renesas, and Infineon, the Arm Cortex-M core is the shared element, and the NPU beside it is where they diverge. Renesas and Infineon build on Arm's Ethos-U55 microNPU, while ST, TI, and NXP ship Neural-ART, TinyEngine, and eIQ Neutron, respectively.

Leading manufacturers are already shipping. ST’s STM32N6 pairs an 800 MHz Cortex-M55 with a 600 GOPS Neural-ART accelerator and is in mass production. Renesas’ RA8P1 combines a 1 GHz Cortex-M85 with an Ethos-U55 rated at 256 GOPS. NXP’s i.MX RT700 is in production, and Infineon’s PSOC Edge E84 is shipping. 

^{Peak ratings are vendor-published theoretical maximums and are not directly comparable across vendors: clocks, MAC counts, supported precisions, and operation-counting conventions all differ. Status and part details from vendor documentation as of September 2026; family names cover multiple SKUs, and STM32N6x5 variants omit the NPU.}

^{1. NXP application note AN14700 (Rev. 2.0) specifies a theoretical peak of 41.6 GOPS at 325 MHz. That clock requires an externally supplied 1.1 V on the VDD2 compute domain; the internal LDOs top out at 1.05 V.}

^{2. Infineon’s architecture reference manual specifies 51.2 GOPS by counting each multiply-accumulate as one operation. Arm counts one MAC as two operations, which yields 102.4 GOPS for the same 128-MAC/cycle Ethos-U55 at 400 MHz. Both figures cover the Ethos-U55 only, not the NNLite NPU.}

The Tooling Is Where the Commitment Gets Made

The path from a trained model to working silicon differs substantially across vendors. TI uses CCStudio Edge AI Studio; ST uses its Edge AI Suite; NXP uses eIQ; Renesas uses RUHMI; and Infineon uses DEEPCRAFT. The model-deployment workflow is part of the platform commitment, and changing MCU vendors can entail software migration costs well beyond the silicon swap.

2. Endpoint AI Changes the Power-Delivery Problem

Alif measured a keyword-spotting model at 6.8 ms and 0.17 mJ per inference through the NPU, compared with 137 ms and 2.62 mJ on the CPU alone. The NPU finishes roughly 20 times faster, returning the system to idle sooner. For burst-oriented workloads, that shorter active window can make peak current and transient response more important than average-power figures suggest.

This behavior lands on rails with little voltage margin. ST runs the STM32N6 core at 0.81 V nominal and 0.89 V in performance mode, and provides a tool for measuring VDDCORE during inference. At those voltages, fast load steps can turn insufficient regulator response or decoupling into intermittent failures.

In higher-power classes, complex processors are driving programmable, sequenced multi-rail power architectures. ROHM’s BD968xx-C PMIC series, paired with its BD96340MFF-C DrMOS, was launched this year as an AEC-Q100-qualified power solution for automotive SoCs, with sequencing for multiple rails. Telechips and SemiDrive have incorporated it into reference designs.

At the MCU level, tighter integration can reduce companion devices without removing the need to engineer the processor rails correctly. TI’s AM13Ex integrates the NPU, Cortex-M33, and real-time motor control on one die and claims up to 30 percent BOM savings by collapsing a multi-chip design.

For a comparison of on-chip regulation, external PMICs, and hybrid supplies, see Powering the NPU: On-Chip, External PMIC, or Hybrid?

3. The Selective Supply Crunch from Mature-Node Reallocation

The 2021 component shortage grew from a broad collision of demand, capacity, inventory, and logistics. The current squeeze is more selective. AI-related power demand is rising, while foundries are reducing or redirecting portions of their mature-node capacity.

AI infrastructure consumes large quantities of PMICs and power discrete components. Demand is tightening 8-inch capacity, while AI applications also consume select 12-inch mature-node processes. Both manufacturing pools support large portions of the analog, power, and embedded BOM. TrendForce puts average 8-inch utilization across the top ten foundries at 88 percent in 2026 (up from roughly 80 percent in 2025) and heading toward 90 percent in the second half of 2026. TSMC and Samsung have also been cutting 8-inch capacity. Foundries are reallocating constrained capacity toward higher-margin power and AI-related products.

Pressure is concentrated in specific subcategories. Eight-bit and many consumer-grade parts show little disruption, while automotive and industrial 32-bit MCUs, analog parts, and high-current PMICs are under pressure.

In August 2026, onsemi told investors that lead times in its growth areas had stretched from 27 to about 32 weeks. ADI has reportedly asked customers to place some orders six months out. Channel reports indicate that some ST MCUs are being quoted as far out as 52 weeks, while some distributors are asking about full-year 2027 requirements. In addition, packaging constraints can extend delivery beyond wafer-fab lead times.

Prices have also increased. TI, Infineon, NXP, and ST announced price increases during the first half of 2026, while TrendForce says foundry prices rose 5 to 15 percent between the first and second quarters, with additional increases extending into 2027.

Use Octopart to check current distributor stock and pricing on MCU and PMIC line items, especially automotive and industrial parts, because shelf inventory determines what parts can support this or next quarter’s build.

4. The Memory Around the MCU Is Repricing

Memory makers are reallocating capacity toward HBM and advanced NAND for AI systems, and low-density parts are feeling the impact. TrendForce estimates that NOR flash contract prices rose 100 to 120 percent in the first half of 2026, while SLC NAND rose 130 to 150 percent. TrendForce expects tight supply to keep prices elevated through the second half.

These parts provide boot, code, and data storage across industrial, automotive, networking, and higher-end embedded BOMs, and they are repricing independently of the MCU. A design that locked its MCU cost early can still see the memory portion of its BOM rise dramatically. When you check processor stock, check the serial flash beside it and consider securing memory pricing on its own schedule.

5. RISC-V Reaches Production MCU Sockets

RISC-V is moving from evaluation boards into production embedded designs. RISC-V International says annual shipments are roughly 2.5 billion cores and describes 2026 as a transition toward design-in and certification. Espressif’s ESP32-S31 entered mass production in July 2026 with dual RISC-V application cores, Wi-Fi 6, and BLE 5.4.

The architecture is also moving into the automotive sector. Quintauris – backed by Bosch, Infineon, Nordic, NXP, Qualcomm, and STMicroelectronics – partnered with SiFive in December 2025 to bring RISC-V processor IP into reference architectures for zonal controllers and ADAS ECUs. Infineon has said it will extend AURIX with a RISC-V family, and ASIL-D-capable RISC-V processor IP is available from SiFive.

RISC-V is already established in high-volume embedded applications and is expanding into higher-performance and safety-critical markets. Arm remains dominant among the NPU-equipped MCU families discussed here. A shared instruction set does not by itself make parts interchangeable, and moving between vendors still means new peripherals and requalification. 

For the second-source and qualification side of MCU selection, see 5 Suppliers Hold 80% of the MCU Market. Where's Your Second Source?

What to Do Before You Commit

AI demand is accelerating four of this article’s five trends, and the board on your bench sits downstream of them. For projects shipping in 2027, qualify parts based on toolchain maturity and current lead time, and prioritize confirmed production over preproduction for near-term schedules. 

Distributors are already approaching customers for 2027 requirements as manufacturers prepare for strong demand, so extend forecasts beyond 12 months for mature-node MCUs, PMICs, and memory on the critical path.

Design the power around the accelerator from the start. When the accelerator wakes up, the rail has to be ready. A rail that cannot handle the load step is a costly problem to discover in the first prototype.