Altium Academy Live | Schematic Hierarchy and Verification
Watch our webinar on Schematic Hierarchy and Verification as part of the Altium Academy Series.
Pin-Package Delay and Via Delay in High Speed Length Tuning Take a look at the inside of some integrated circuit packages, and you’ll find a number of wires bonded to the semiconductor die and the pads at the edge of the component's package. As a signal traverses makes its way along an interconnect and into a destination circuit, signals need to travel across these bond wires and pads before they are interpreted as a logic state. As you look around the edge of an IC, these bond wires can have different Read Article