Keynote: Eric Bogatin erklärt, wie Sie verhindern, dass Ihre Leiterplatten rauschen wie ein defektes Autoradio – AltiumLive 2022

Ein Schaltplan sagt nichts über SI, PI oder EMI aus. Erst wenn man die idealen Verdrahtungen und den weißen Raum des Schaltplans in das physische Design eines Layouts überträgt, erwachen diese Probleme zum Leben. Und das Einzige, was die physischen Verbindungen in Ihrer Leiterplatte bewirken, ist Rauschen und eine Verschlechterung der Systemleistung. Ich konzentriere mich hier auf die Überlappung der drei Welten von SI, PI und EMI: die Designmerkmale, die eine Dreierkombination bilden und zu allen drei Problemen beitragen, und wie solche Probleme reduziert werden können.

Zusätzliche Ressourcen:

• Vernetzen Sie sich mit Eric Bogatin auf LinkedIn
• Eric Bogatin über schlechte Gewohnheiten beim Leiterplattendesign – AltiumLive-Keynote
• Schlüsselmethoden zur Kontrolle von Rauschen, Interferenzen und EMI in Leiterplatten – Hartley

Transcript

Introduction:

Eric Bogatin is currently the Dean of the Teledyne LeCroy Signal Integrity Academy at bethesignal.com. Additionally, he is an adjunct professor at the University of Colorado Boulder in the ECEE department. Bogatin received his bachelor of science in physics from MIT and master of science and PhD in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices. He has written six technical books in the field and presented classes and lectures on signal integrity worldwide.

In 2011, his company, Bogatin Enterprises, which he founded with his wife, Susan, in 1990, was acquired by Teledyne LeCroy. After concluding his live public classes in 2013, he devoted his efforts into creating the Signal Integrity Academy, a web portal to prove provide all of his classes and training content online for individuals and for companies. Please welcome Eric Bogatin.

Eric Bogatin:

Hi, everyone. It's so good to be back at Actium Live. Thank you very much for the kind invitation to present again this year. I'm going to be talking about How to keep your boards from screaming like a Banshee, which is really about looking at some of the pathological problems that can arise from design and what we can do about them. I just wanted to emphasize one quick message about me. I wear a number of hats. I am full-time teaching at University of Colorado in Boulder. A lot of what we're going to talk about today is topics that are covered in one of the classes I teach the printer circuit board design class. I'm also a fellow with Teledyne LeCroy and still continue to do some webinars about best measurement practices, and still technical editor of the signal integrity journal. And if you have an visited us before you definitely want to check out signalintegrityjournal.com.

On that note, I also wanted to leave you with some resource materials. There's a limited time we have today to cover the important topic. And so I wanted to give you an opportunity to seek other information if you are interested in this topic. It's really opportunity to provide some blatant advertising for some of the other content that I've created. First of course, are my textbooks. A lot of what we're going to talk about is actually covered in my latest book from Artech. This is my guide to prototype breadboard and PCB design. It just came out a few months ago.

And if you're involved in prototype design, you definitely want to check out on that book. And then my other textbook, Signal and Power Integrity Simplified, also covers some of the background information about inductance and noise that we're going to be talking about today. But wait, that's not all. There's more. I've started a podcast now with Signal Integrity Journals called Signal Integrity Journal Fundamentals. It's really a chance for me to have a conversation with some of the experts in the industry, a chance for them to talk about some of the work there involved in, and a chance for me to ask questions. I get a captive audience of one-on-one time with an expert and you get to listen in on my conversation with industry experts. So check out the podcast series. It comes out every two weeks.

But wait, there's more. I mentioned that I do webinars with Teledyne LeCroy and all of those webinar are posted on the bethesignal.com website. So if you go to the website on the left hand side, you'll see a few different categories of webinars that I've done. We have a whole series about scope applications and measuring different qualities of Signal Integrity with source scopes. We have a whole series just about power integrity, another one on network analyzer, fundamentals, and S-parameters, and finally, a whole series of webinars just about TDR applications.

So be sure to check out some of those free webinars. You can click to expand the categories. You'll see the list of webinars. You can go to the landing page and then view any of the webinars that you're interested in. And of course you can download a copy of the slides as well. Oh, but wait, there's more. As courtesy of Teledyne LeCroy, we're providing a special opportunity for all Altium Live attendees to get a complimentary three month subscription to the Signal Integrity Academy. There's a collection of about 200 hours worth of training on Signal Integrity and Power Integrity topics that I've done over the years, that have been recorded normally under a subscription, but if you go to the Signal Integrity Academy website and you click on the category for subscriptions, you'll see a heading for three month subscriptions. And if you fill that out and use promo code, ALT21, that'll get you a three month complimentary subscription. You'll get complete access to all the content there.

So a lot of what we're going to talk about today is covered elsewhere. And in the limited time we have, I'm not going to feel guilty not being able to cover all the important topics because there is additional reference material available for you. So here's what we are going to talk about. I want to spend a couple minutes talking about the root cause for crosstalk and then look at path cases. These are the extreme cases any one of which can cause product to fail. And we're going to explore four different examples of pathological crosstalk all with kind of similar root causes, and that's why they're kind of grouped together. These are all examples from the course that I teach. I'm going to show you some of the boards that I have my students build. Some of the measurements and how we interpret those measurements to see how we can screw up layout and cause these problems and then of course what we do in the layout to reduce these problems.

Well, before we get into the details, just a quick summary of kind of where we're at and some of the issues related to how do you make these design decisions? When I go around and I do webinars or when I used to do it live, I would get questions all the time about, "Well, what's the right way of doing it? How do you make design decisions?" And wanted to offer my perspective and then some recommendations. So here's what I think is going on. Most of the decisions that we have to make are really a balance of different trade offs. On the one hand is performance. We'll see noise. We're trying to affect the noise at some cost. And the cost is a dollars for components, but there's also cost in terms of risk and schedule.

In these days we worry about the supply chain as well as issues about what some of the past history of the company was that has molded the decisions in the strategy within a company. When we engineer interconnects, the number one first most important thing we care about is connectivity. Making sure all the terminals that are supposed to be connected are connected and those that are not supposed to be connected are not connected. Once we've established that connectivity, then interconnect design is really about ... in terms of performance is really about reducing noise. That's what we want pay attention to, but unfortunately if you haven't measured the noise in your system to know the impact your decisions have made in it, it's hard to learn from past designs. We often say that, "Well, the last board I did it worked. So I must have done things right." But if the noise is below an acceptable level and if we're not measuring it, but we just use the criteria of it worked as the criteria of we did it right, your design may have worked in spite of your design choices rather than because of them. And so we run the risk of learning bad decisions because we don't have good input information.

Of course, if the test vectors that you chose to use to test the product, to decide whether it works or not, if they don't cover enough of the worst cases, then you really don't have confidence how robust the product is because of your design decisions. And if there's some test case there that will cause the product to fail, guaranteed, one of your customers is going to find it. So what do we do? How do we make design decisions? And here are just a few guidelines. I cover a lot more of the details in one of my textbooks, but here are a couple of recommendations. First is I think it's really important to understand the design choices based on the fundamental principles. And once we understand those fundamental principles, we want to quantify them and put in the numbers either by a rule of thumb, a rough estimate, or even a numerical simulation.

We want to be able to explore design space, to evaluate the different decisions using either virtual prototypes in simulation or calculation or using well-characterized real prototypes. And I'm going to show you a couple of examples of using well-characterized real prototypes just to show kind of qualitatively what the difference is in the performance or the noise ways in different design decisions. Good ways and bad ways. And then finally, I think that it's important to be aware of those design decisions that will result in lower noise if they have no cost impact. If they're effectively free and they give you some performance or noise reduction, they're things that have a really good return on investment and you always want to be doing that. I think we want to adopt these design paths as habits, and that's what we're going to talk about today.

So let's jump in and let's talk about crosstalk. Whenever you have a problem you want to solve, the first thing you have to know is what's the root cause? And when it comes to crosstalk, the root cause of crosstalk is really about the electric and magnetic fields coming from an aggressor onto a victim. We call these the mutual electric field lines or the fringe field lines from the aggressor to the victim. And it really comes down to engineering, designing the interconnects to engine near those fringe field lines, fringe electric magnetic field lines to reduce them. And if we can reduce those fringe electric magnetic field lines, then we'll reduce the crosstalk. And that's where it's important to understand a little bit about electric magnetic fields. Well, unfortunately some problems are a little bit too complicated to solve quickly based on fields. And that's where we approximate the electric fields in terms of capacitive coupling and the magnetic fields in terms of inductive coupling. And so we'll sort of use them, interchange a little bit. The real fundamental root causes about electric and magnetic fields. We approximate them to get the answer faster sometimes with capacitor and inductor circuit elements. But once we understand the behavior of fields, then we can immediately see two physical design features that will reduce the crosstalk, and here is one of them.

I chose just a couple of microstrip lines is the example just to illustrate the principle. We've got an aggressor signal and return path here, and I'm using very nice wide continuous return planes in these examples. So we got an aggressor and a victim, and you can see the electric field lines from the signal on the signal line. Those fringe field lines are the big long snaky field lines that go from the aggressor to the victim and they spread. I've kind of exaggerated here to illustrate this. Same thing for the magnetic field lines. Here's the example of the magnetic field lines from the signal and its return path. And some of those field lines also go around the victim. Those are the fringe magnetic field lines. Those are the fringe lines that we want to reduce. How do we do that? Number one is, hey, pull the two traces farther apart. That's the easy one. The second though is we can engineer the interconnect. We can sculpt those fringe field lines by bringing the return path in closer proximity to the signal line. If we do that, we'll force the fringe field lines, the fringe electric, and the fringe magnetic field lines, we'll force them to be closer to the vicinity of the aggressor. They won't spread out quite so much.

So here are two physical things that we can do in order to reduce the extent of the fringe fill lines, reduce crosstalk. But both of these examples, I'm assuming that our return path is a nice wide plane. Which do you think in this environment is going to generate more crosstalk? Capacitive or inductive coupling? Well, when I ask this question live, I always get a pretty even split in the audience. Half the audience says it's inductive coupling that's more dominant, the other says capacitive coupling that's more dominant. Well, in this environment where we have a nice wide return plane, they're both comparable magnitude, they're both equally important. We have to worry about both of them, but if we do anything to screw up that return path so the return path is not a nice wide plane, but is maybe a single lead and a package, or a single pin in a connector, or a gap in the return plane. If we do anything to screw that return path, then the inductive coupling will dramatically increase compared to the capacitive coupling and that becomes a pathological problem. And that's what I mean by pathological crosstalk. It's when that return plane is not a nice wide continuous path, the crosstalk will dramatically increase and it's dominated by inductive coupling.

So we're going to look at a number of cases where the crosstalk is dominated by inductive coupling. Where we so much crosstalk it's really pathological. Here's one example of what I mean by that. And we'll see this a couple times. This is a chip. It's got five I/O on it. Here's the package over here, they're driving the I/O , they're driving lines on a circuit board, and then this one over here ... So these four are going to switch. We're going to look at one of the sick signals from one of these lines and this one is going to be ... its output is going to be low. That means normally it should be zero volts, but any voltage noise we measure on it is going to be noise, unintended signal. And it's going to come from these guys switching and their currents flowing through this common lead in the package. And this lead has some inductance.

Here's the solder ball or the solder joint under the board and here's the plane on the board. And so when we have this output low, we're going to measure the voltage coming off of that output over here. It is literally connected to the end channel over here if this is low. It is literally connected to the VSS pin on the dye. And so when all of these switch, we're going to have their di/dts through this common lead into this high inductance region because it's not a plane. It's a lead in the package. We've constricted the current through a narrow path increasing the total inductance in that path. When all these switch, we're going to get voltage noise over here and we're going to see that as the voltage noise on the quiet line. And here's what we measure.

So here is the signal of one of these I/O that's switching. And as that I/O current flows through the return path, we're getting a voltage on this side compared to this side. This is where we're measuring the voltage between the signal and the local return over here. We're going to see this voltage over here connected through the end channel into the signal line. We're going to see the voltage there and that's the voltage noise that we measure. This is pathological crosstalk. This can be extremely large amount of crosstalk. We'll see some examples of that because of the inductance in this loop, coupling to the inductance from other aggressors. That's what we mean by pathological.

Well, I said right at the beginning that in order to evaluate the impact our design decisions have on performance in particular on noise, we have to be able to measure the noise. And I'm going to introduce you to a couple of really important measurement techniques in order to measure this kind of pathological noise. Now, I covered these in a lot more detail on some of the webinars that I've done with Teledyne LeCroy. Those webinars are really about best measurement practices. I wanted to emphasize here some of the layout decisions, the impact on performance, and then some examples of the measurements, but here's a really important technique we're going to use to do some of these measurements of the noise generated by layout decisions. The first one I want to introduce you do is using one of the output pins of the digital devices as a sense line. We call it a quiet low.

So here's an example of an output driver for some device. In this case, we're going to be looking at micro controller or we're going to be looking at a small digital logic devices. And so here's one of the outputs [inaudible 00:17:36] device. You get the end channel connecting, here's the output pin and it's connecting through the P channel to the internal VDD rail and also through the N channel to the VSS rail on the dye. So here's the chip and there's multiple I/Os on the chip, and then here's the package that's enclosing it. We're going to use one of the I/Os and we're going to peg its output as low. That means that we're turning the N channel on and the P channel off, that means that the I/O for where that particular pin is now literally ... This N channel is literally an analog switch and we have connected that output pin to the internal VSS rail. And so that output pin has now become a sense line for the VSS rail on the dye itself.

When we're over here and we're measuring the voltage on that sense line compared to local ground, what we're really measuring is the voltage on the VSS rail here compared to the local board ground. And if we have a voltage drop in this path, we're going to see that in the series with the voltage we measure in the output pin. And so we have to kind of get used to these ideas of ground is not universal in a board, in a system. There's local ground that is a reference to the local devices that's on the dye. That's the VSS rail on the dye is local ground. And where we measure on the board, there's local ground that we're using as a reference to measure the voltage on some other point. And so when we use a quiet, low as a sense line, we're measuring all the noise generated in that loop from currents that are flowing from the return path, the inductance or impedes the return path or induced noise in this signal return loop located from the point at which we're measuring on the board through the device, the leads in the device, and then back through the return path. So we're going to use this now as our sense line. Let's take a look at an application of that. And the first one we're going to look at is this board to illustrate the impact of not having a nice wide continuous return.

So here's a board. That's one of the examples that we use in my class. It is a circuit that's got a little clock generator over here that's drive two hex inverter circuits. Here's one of the hex inverters, here's another one. There are six, obviously six inverters. One of them is going to be pegged low so it's output is always low. It's going to be a sense line of what's going on on that dye. And that tiny dye on the inside of that device is going to be a quiet low. One is going to be a quiet high. We'll talk about that next. One is going to be triggering from the clock over here that we're going to use to trigger our scope. So we're going to look at the output of that into the scope and that'll trigger and tell us when are all of these switching? And then three of them are going to drive LEDs and resistors. So we get about 30 milliamps of current switching through each of those. So three of them switching. That's about 90 milliamps of current that's going to switch through this device and we're going to look at the quiet low, the voltage on the VSS rail on the dye and the crosstalk through the rest of the board from that sense line, that quiet low path when we have these 90 millions of current switching.

So we have one region of the board where there's no return plane underneath and we have the rest of the board where there's this nice wide continuous return plane. And we have exactly the same circuit over here driving the same three LEDs with a quiet low and a signal coming out to switch to the scope and a quiet high as well. So we're going to drive those three LEDs. We're going to look at the noise on the quiet low line where we don't have a plane and when we have a plane, and you'd expect a lot more inductively coupled crosstalk because we don't have a nice wide plane here.

Over here, we have a nice wide plane. We shouldn't see very much inductively coupled crosstalk on the board, but we still have that package there. So we'll still see some of the ground bounce from the package itself. Here's the measurement setup. Here's our board. I got power on it. We're going to be using one of the I/O to trigger the scope. And so this is channel one of the scope, the yellow trace going to the scope. This is going to be the quiet low for the region of the board where you have a nice wide plane. So this is going to be the noise on the dye mostly due to the package lead inductance. That's as low as we can get.

Everywhere else there's very little crosstalk in this region on the board because we have this nice wide return path. We've got low mutual inductance between the quiet line and the rest of the aggressors elsewhere on the board. Whereas in this region, we're going to have the 90 millions of current flowing through the signal and the return path, quiet low that we're going to measure over here, that quiet low, we're going to see the package noise plus the mutual inductance from ... And you can almost imagine this loop. Here's the ground connection over here. Here's this big loop going through here, and it's going to come through here. Here's the ground path. It's going to come all over here. So we have this one big loop that is now going to be picking up noise on this region of the board because there's no closely coupled a continuous return path.

So let's take a look at the relative amount of noise in these two cases. Now, I use this trick. Whenever I have more than one probe, I like to color code my probes to make it easy in order to remember which one is connected where and they're color coded with the traces that I see on the scope. Look at the test pattern that I use.

I have this test pattern that has a signal pin and three returns. And that allows me to use that very small little spring ground clip so that I have a short loop on the tip of the probe. It reduces signal distortion, number one, and number two, it also reduces the probe to probe crosstalk which can be pretty considerable. Mutual inductance be to we the probe signal returns. And keeping the very short ground spring tip means I have very low loop inductance here, very little probe to probe crosstalk. And so this test pattern facilitates the use of these really small little spring ground tips. Okay. Let's take a look at the measurement. And here it is. So here in yellow is the trace going into the scope. That's what's triggering the scope. That's telling me when all of these four I/O are switching. Remember one is a quiet low, one is a quiet high, three of them are going through these LEDs, and then the fourth is coming off to trigger the scope. So here's the scope being triggered. In this case, it's a five volt signal.

Now, here in the red, that's this guy here, he's on the quiet low for the region where we have a nice wide return and you can see, Hey, I've got some ground bounce. That's VSS ground bounce. And how much is that? Oh, my gosh. Let's see. It's 200 millivolts a division. So there's 200, 400. That's 500 millivolt peak to peak. That's fundamentally limited by the inductance in the leads in the package. But in addition to that over here, I've got all of the mutual inductance between this large signal return loop for the quiet line and the other signal return loops of the aggressors over here. They're all coupling together here. And look, I'm almost tripling the amount of crosstalk. This is a visceral example of why it is so important to use continuous return plane on the ... in your boards to reduce the inductive coupling between aggressors and the victim ones.

We still have it in the package. There's not much we can do about that, but we can reduce it elsewhere on the board. Second example I want to look at is about power rail collapse. So here's a really a simplified version, a schematic of what's going on in the power distribution network. Here's the I/O or the chip. That's going to switch modeling kind of as a current source here. There's the voltage regulator module over here. And between the VRM and the paths on the dye, there's all the interconnect inductances. Well, I've added here a little capacitor, a decoupling capacitor because we want to use that capacitor as kind of like a [inaudible 00:26:28] as a local charge reservoir so that all the switching current, the di/dt current that's going to flow through this device is all going to come from this capacitor. And during that short di/dt time and that current that flows, it's not a lot of charge. We just want to make sure we have enough capacities here so the voltage doesn't drop very much to do charge depletion. And so it can act it's kind of a local reservoir, local VRM for our device that switches, but we still have this residual inductance, path inductance from the pads on the dye to where that decoupling capacitor is placed. And it's this inductance that's going to influence the switching noise.

All of this inductance here are totally irrelevant because all the di/dt is going to flow from the capacitor. None of it is going to be flowing over here. And so it's only this path inductance that we have to worry about. And what's the impact of that? So all this is going to be at the five volt VCC rail. When this current flows, I get my di/dt. That means through this inductance in the power path, I have a di/dt. And that means that from here to here, I have a voltage drop. That means I'm going to see a droop over here on the dye. And if I could look over here on the dye, this is what I would see. I would see the nominal voltage. And when that current switch is, I'm going to see a very sharp voltage drop because of the di/dt through the inductor. The smaller that inductor is the less, the voltage droop that I'm going to get. And how do we make that smaller? We physically move the capacitor in close proximity, but in order to see this, I have to be looking at the voltage on the dye itself. This could be the trace leading to the package plus the package loop inductance.

We cannot see inside the dye to measure that. How are we going to do that? That's where our sense lines come in. So we're going to use one of those I/Os as a quiet high. We're going to take another I/O, we're going to turn the P channel on so the output literally connects to the VDD or the VCC rail on the dye. So when we're measuring out here, what we're going to be measuring is the voltage on that output pin, that sense line of the VDD or VCC rail here on the dye relative to the local board voltage, the ground on the board. But of course, remember if we have voltage over here on the VSS, this whole chip is going to be bouncing up and down relative to the ground.

If we measure the voltage over here, in addition to the voltage droop from the current flowing through this inductance, in addition to that voltage droop, we're going to see the ground bounce from the board if we measure it over here. And so we want to be careful when we measure the voltage on the VDD rail relative the local ground on the board. We also want to measure the VSS rail rail through the local ground on the board. And then in order to get the voltage between them, the voltage on the rail itself, that drop in voltage, we sometimes refer of that as rail compression. To get that rail compression, we want to take the difference between the voltages. So that rail compression is the voltage difference between that VDD or VCC voltage on the high side minus the VSS rail. So we're going to do both a quite high and a quiet low measurement. So now let's see the impact. And we said it's that location of the capacitor and the inductance from the pads on the device to the capacitor. That's the inductance that's going to influence that voltage droop.

Let's see the impact of that now that we have a way of measuring it. So here's another set of boards. Similar kind of structure. I love these hex inverters. They're great little vehicles in order to create some di/dt and also let you see voltages with sense lines. So here's my little clock chip over here. I'm going to drive similar kind of behavior. I'm going to drive three of the I/O. Here are some LEDs that they're going to drive and current. So I'll get about another 90 million of di/dt through it. We're going to have one of these I/O as a quiet low, so I'll measure the VSS rail on the dye. And one's going to be a quiet high, and I'll measure the VDD rail on the dye relative to local board ground. And I've configured three different physicians for the decoupling capacitors. So here's the power rail and here, the decoupling capacitors are really close, but I've built a couple of other boards where I've moved those decoupling capacitors farther away. Oh, my gosh. Look how much farther away they are? In each case, we've increased this inductance. We're going to increase the voltage droop that going to see. We're stuck with the package lead inductance in here. We're still going to see package lead inductance fundamental limit, but we'll see the impact, the additional noise from having the location of the capacitors.

Now, keep in mind that the capacitors, we call them decoupling capacitors because they are literally decoupling all of this board level inductance from the voltage droop that the device is going to see. They're the local VRM. All of this inductance is totally irrelevant in looking at the voltage drop on the dye. What's important is the inductance in this path. And so this one is going to be a little bit more and this one's going to be quite bit more. Let's take a look at what those measurements of increased voltage noise are.

Again, here's my board. It's instrumented. I've got my ground spring tips on all the 10X probes. Here's the signal that's going to go to the scope to tell me when are all those I/O switching? Here are those I/Os switching. This is why high, here's the quiet low. There's a continuous plane underneath everybody here. So we've minimized the ground bounce noise from the board, but of course we still see it in the package and here are the results.

So here is the I/O switching. So I'm using that to trigger my scope. I know when they're turning on or turning off. Here's the quiet low. This is the VSS bounce on the dye itself. Our scale here is half a volt, a division. So we're still talking about that two, 300 millivolt kind of noise that we're going to see on the dye because of the di/dt and the package lead inductance. But here is the voltage noise on the quiet high. This is the VDD rail. Now in this particular example, we've got ... This is a 3.3 volt rail and this is a half a volt per division. So look at that. That voltage droop is 1.2 volts out of a 3.3 volt rail. That is a huge voltage drop. We are effectively turning off the transistors when that voltage gets so low over here. That's why it's kind of a funny shape, that's why we see this kind of behavior over here. We've literally gotten such a large amount of voltage droop on that power. We're turning off the transistors. Huge, this is pathological voltage noise.

Now, what we really want to see is the real compression between the VSS and VDD on the dye. So numerically, we're going to take these two and take the difference, and here it is. The gold colored trace here is the difference between the VDD noise minus the VSS noise. And you can see it's that 1.2, 1.3 volt dip or droop because of the inductance in this long path. Now that we've got a method to measure it, we can compare the voltage droop for these three different locations of decoupling capacitor. And what do you think we're going to see? Well, it shouldn't be a big surprise. Here is the real compression noise. This is for the capacitors far away. It's that 1.3, 1.2, 1.3 volt of droop. Here it is when the capacitors are closer and here it is at their closest approach.

Now, there's not a big difference because we're still fundamentally limited. Here's like a half a volt of rail compression noise. We're still fundamentally limited by the large loop inductance in the package leads because in these packages, there's SOC package, we've got the ground down here, we've got power way up here. So we have this huge loop inductance internally in the power distribution path even though the decoupling capacitor is out here. And so that's giving us that half a volt drop. That's why you just can't do much faster edges with these packages because you're just going to get more and more ground bounce and power [inaudible 00:35:11] noise with the large loop inductance in the package. Well, if you think about it, look, I'm telling you just 1.2 volts of voltage droop on the dye for or 3.3 volt reel. The first thing you should say is, "Wait a minute. I've built hundreds of words. I've never seen that. How is that possible?" Here's how it's possible.

Remember that model we introduced for the power distribution network. And we said, "Here's the dye. Here's all the I/O switching." We're looking over here at the dye itself and looking at the voltage noise on the dye, which is where it really matters because of the di/dt through that inductance from the pad on the dye out to the nearest coupling capacitor. All of the di/dt is flowing in this path from the capacitor. We're not getting any di/dt through this path over here. And so we're going to see a constant voltage if we look here, or here, or here on the board. But if we look here on the dye, we're going to see it. And sure enough, here I've instrumented. I've added another probe.

So one of the advantages being a fellow at Teledyne LeCroy is I get as many probes as I want. And here's our fourth channel high performance scope. Now, I've added the fourth channel. Again, using the color coding here, here's green. That's going to be the fourth channel. And that is looking at the 3.3 volt rail on the dye itself and here are those measurements all at one time. Here's the I/O switching the scope. It tells us when the I/O are switching. The red is the quiet low. That's looking at the VSS real bounce on the dye. The blue is the VDD quiet low, that's ... or quiet high. That's telling us the VDD on the dye relative to the local board ground. The difference between them is the real compression. Huge amount here of 1.2, 1.3 volt rail compression, but here in green, this is everybody is on the same scale. In green is the voltage on the 3.3 volt rail on the board. We're looking over here we don't see this large amount of noise.

In fact, if we looked here, we wouldn't see very much noise either because it's that charged depletion from the capacitor that is going to cause the voltage to droop just a little bit. It's all in this path that we're getting that voltage drop. And unless you instrument your board in order to measure the on dye voltage, you'll never see this huge amount of noise that's present on the dye. Just because your board worked, whatever that means, doesn't mean the design decisions you made were the right ones, unless you're able to measure the noise precisely where it's happening in order to evaluate the impact some of your design decisions have on the noise.

Okay. Third example. This is now about four-layer boards and about via-to-via crosstalk. Also in my book on prototypes, I have an example of a number of different options for how you choose the stack up for a four-layer board. I'm not going to spend time going through options here. I'll leave this as a teaser to ask you which is better. Now, when I show this around, the common comment I have is, "Oh, I use this particular. I use X, Y, Z design and the board worked. So that must be the right one." And someone else says, "No. I use this design and the board passed EMI. So it must be the right way of doing." "No. I use this design and the board passed. So this must be the right way of doing it." Just because a previous design that you used that had a specific feature in it and the product worked doesn't mean it was the best solution. Remember, it's important to go back to some of the fundamental principles to understand what motivates the design decisions and then consider putting in the numbers to see what the magnitude the effect is and maybe building some prototypes.

So I'm going to show you an example of the impact of using the two inner layers as planes in the stackup either this option or this option. And then for this option, what the problem can be if this is a power plane and this is a ground plane when signals transition from one layer to another. So here is the it impact from via-to-via crosstalk when we have this kind of a stack that we have ground and power layer inside the board. And we're going to look specifically the case of a signal that's on the top layer and transitioning to a signal on the bottom layer and look at what happens to the return current. So here's that stack up. Here's layer one, two, three, four. Signal layer on top, here's the ground plane, here's the power plane in this stackup. So when a signal is on the top layer, where's the return current for it?

Well, the return current is the plane adjacent to it in layer two. Signal return, signal return, signal return. When the signal gets to the bottom layer and it's propagating along, where's the return path for the current ... when the signal is on layer four? Well, it's on layer three. The power plane is signal return, signal return, signal return. We provide this beautiful wonderful via to provide a path for the signal to go from layer one to layer four, but how does the return current flow from layer two to layer three? And the answer is it flows through the impedance these two planes create. We call these two planes a cavity. Any two planes are a cavity. Whether they're both ground planes or a power and ground plane, it's a cavity.

When that return current transitions from ... it's going signal down here, it's flowing return. And then return current flows through the two planes back up again, but now we've just launched a signal into this wide transmission line that's the cavity. It's going to propagate and there's going to be a voltage difference between these two planes based on the current that flows between them and their impedance. And that current is going to rattle around and that's going to generate noise in the cavity. And we're going to see that if we have another innocent victim via going between the top and the bottom. And if we have another victim line going through here, it's going to have induced voltage noise due to the noise in the cavity. And of course the cavity has the potential of causing the cavity noise, it has the potential of doing some other problems.

So if we have a stock up that has power and ground planes, there's some impedance between those planes. When the signal transitions from one layer to the next, the return current has to flow through that cavity and flowing through that impedance of that cavity is going to generate noise. And any other signals that pass through that cavity are going to see that noise in the cavity as well. When that return current goes through the impedance of the cavity, we get a voltage and that voltage is going to be seen on victim via as crosstalk. And if we want to reduce that via-to-via crosstalk, we want to reduce the impedance of the cavity. And the number one way of doing that is adding a shorting via between the two planes. But of course, in order to add a shorting via that provides a low impedance between the two planes, the two planes have to be the same voltage. Can't do that if it's power and ground.

If it's power, we can't have a shorting via between there. It's only if these two planes are ground and that's the motivation to select the two planes inside the board as both ground planes because it gives us that option, that opportunity to add a shorting via which is the lowest impedance path between those two planes for providing a low impedance for that return current to pass. That means low voltage noise in that cavity and that means low crosstalk between vias.

So I'm going to illustrate for you the impact of ... or the consequence of not having return vias versus having return vias. Now, while we're talking about it, I hear everybody say, "Well, that's okay. I'm just going to add decoupling capacitors between power and ground." Perfectly fine to do, absolutely something to do, but what you're really doing is you're providing a DC block to a couple of villas. In other words, you go up to the top layer from one plane to the other plane through a DC blocking capacitor. And so you're using the DC blocking capacitor to provide a shorting via between the two planes and guaranteed, no matter how good you are at engineering, your DC blocking capacitor placed on the top between theirs. It will never have as lower loop inductance as a direct shorting via.

So you're hoping that your DC blocking capacitor is going to provide a low impedance between the two planes. It's not about the capacitance. You're just using it as a DC block. It's the via path that provides the low impedance and guaranteed you're never going to have as low a loop inductance in mounting a capacitor to the board as a direct shorting via between the two planes. And so if you really want to reduce the noise, the best way of doing it, unless you have a strong compelling reason otherwise, you want to make them the same voltage plane and add a shorting via. And now I'm going to show you the consequence of that.

So here again is another test board. So this is the bottom of the board, here's the top of the board. It's a four layer board. This is the stack up. We got signal on the top, signal on the bottom. We have a ground plane on layer two and we have a power plane. In this case, it is floating. There are absolutely no connections to it. Now on the bottom, we have two hex inverters and we're going to drive all six of those I/Os on each one. So 12 I/Os are going to be driving through transmission lines. This is here. We are on the bottom. To a via, to the top. And we pick it up from the top and it's going to go through this LED and resistor. So we can see that it's on and we're going to get about three million current through each one of these.

So we have 12 of these that are going to be switching. We got six over here, we got six over here. And here is one line that's in the middle that is just a victim line. Here's the probe connection that will probe from the other side, here's the signal path going through a signal via, and then it comes up and here it is on the other side and it continues along. Now to layer to the ground plane. And so it's literally just a via through the board that's shorted. And so it's a little loop, it's a victim loop.

So we're going to drive these 12 I/Os. They're going to go through the signal vias, come up to the top drive LED. So we're going to get this 12 of them, 20, 30 million each. That's a third of an Amp of di/dt current that's going to be flowing through the two planes and into the cavity. And we're going to look at the cavity noise with our victim line over here, and they're going to switch. The rise time is pretty good. I use pretty fast I/Os here, fast as I could get. It's about a nanosecond rise time. So in addition to all of the signal vias that are passing through from the bottom to the top, I've also added on this board return vias. So return vias in close proximity that are shorting out between layer two and layer three on this board. So this board and the stackup, I'm just shorting between these two planes. So even though the return current goes through them, the return current is going to go through those shorting vias as well. So I don't expect to see very much noise on this poor victim via.

Now, to compare this with the case of floating power plane, I built an a second board. This is one of the boards we use in our class. So here on this board, top view, we've got return vias because we're using the layer three as ground, but here layer three is purely floating. There are no return vias. Now I added pads between layer two and layer three so we could put a capacitor if we wanted to, but I'm not showing you any capacitors in this board. Those two planes layer two and layer three ground and power on this board they are purely floating, there are no return vias. Otherwise there are identical circuits. Exactly the same hex inverters, the same clock, the same simultaneous switching, the same 50 Amp resistors here, the same 30 milliamps of current, the same LEDs, the same victim line, the same signal lines. The only difference is return vias here, no return vias over here.

Now, let's look at the result. So here is the case of no return vias. So when the signal goes from layer one to layer four and the return current has to flow from layer two to layer three, how's it going to get there? It's going to get there through the impedance of that cavity. There's a DC block ... DC opened between these planes. They are not connected. Layer three is floating, but there's still impedance between these paths. And so as that return current flows, we're going to get voltage noise in the cavity and there's our poor victim via that's over here that's passing through that cavity and then shorting over here. We've got loop here. It's going to pick up that voltage noise in the cavity, and here it is.

So here's the scale. This is a 200 millivolts per division here. In this case, it's a five volt swing. That's the signal came in at hex inverters. It's about 30 milliamps per 360 millions altogether switching in about a nanosecond. And here's the voltage noise on the victim line. Peak to peak is about a little more than 600 millivolts of noise on that victim line with 12 of these I/O switching. And because of the dimensions here, the edge, that nanosecond edge extends about six inches in spatial. The whole board is only three inches. And so that means basically the whole board is an equal potential. Everywhere any instant of time, we're going to measure the same voltage. And so this noise that we're measuring here on our victim line over here, we would measure that anywhere we go on the board between the two planes. We'd measure that 600 millivolts of noise. And any where we had our signal vias transitioning, they would all contribute more and more current to the impedance of the whole board and we would see that as more and more voltage noise on the board.

What happens when we have our return vias in the board? Well, here's the case. Here's the return vias, here are the no return vias. And here, same scale, this is the noise that we see with no return vias. This is the 600 millivolts and here in pink is the voltage noise of poor victim sees when we have adjacent return vias. Dramatic reduction in the amount of crosstalk when we have the return vias. That's why we want to use the two inner layers as ground because it gives us that option of adding the shorting vias between the planes. Those shorting via reduces the impedance and reduces the voltage noise when we have signal switching and it reduces the voltage noise in the cavity as a whole.

Yeah. You can have a poor substitute. If you have to have a power and ground plane, you can use DC blocking capacitors to make shorts between them, but it's never ever going to be as good as adding direct shorts. And that why I always say unless you have a strong compelling reason otherwise, if in a four layer board you want the two inner layers as the planes, make them both ground because it gives you that opportunity of adding return vias, and dramatically reduces this pathological noise in the cavity. Okay. Last example. We're switching gears a little bit. We're going to look at radiated admissions from a board. Now, unfortunately, all I can really measure my lab are near field emissions, not far field. To do far field you need an [inaudible 00:51:44] chamber because you have to get far enough away so you're in the far field. And for 100 megahertz kinds of frequencies, that's ... you have to get more than 10 feet away.

What that means is when we look at the near field radiated admissions from a board as opposed to the far field, we're looking at not the far field radiation pattern, but we're looking at combination of all of the different dipoles, and quadruples, and hexapoles, and octopoles that are radiating in close vicinity to the board. Each one of those different patterns of current distribution falls off at a different rate. That means the farther way I go, the incredibly small some of them are. If I go far enough away, the only term that's going to survive, the only kind of antenna I'm going to see is a dipole antenna. That's what survives to the far field. All of the other higher order antennas, the more complex shapes, their radiated patterns drop off much faster. So if I look in the far field, I'm going to see only the dipole radiation, but if I look in the near field before they've had a chance to die off, I'm going to see all of them. 

So we have to be really careful when we do these kinds of measurements that I'm going to show you to keep in mind that we're looking at near field emissions and not far field emissions. Some of the near field emissions, some of those higher order emissions, higher order shapes of the current patterns, some of those higher order shapes, their radiated emissions are going to drop off a lot faster. We'll never see them in the far field. So just because I see a lot of noise in the near field is not always an indication that I'm going to have a far field in my problem. But if I have a far field problem, if I'm seeing this term in the far field, guaranteed I'm going to see it in the near field. So there is a lot of value in looking at the near field emissions, but you got to keep in mind that, okay, it can be a little misleading. Just because I see near field emissions doesn't mean it's far field, but the advantage is I don't need a chamber in order to these quick pre compliance tests.

So here's the test we're going to do. We're going to look at near field emissions. And here are a couple ways of doing the probing for near field emissions. So here's a commercial probe, small loop. So we are looking at ally induced noise in a loop. It's inductive coupling, but it's in the near field. And some of that near field emissions can propagate into the far field. So here's a small loop, one way of testing it. Here's my homemade loop. It's just a 10X probe and shorting the signal in the ground together. I've got a loop and now I'm picking up the induced voltage because of the magnetic field lines coming from the board that are also going through this loop. Here's another way of looking at pre-compliance testing. This is looking at the common currents on external cables. And I've got a couple webinars I've demonstrated these different measurement techniques.

Well, we're going to use this method here. This is my favorite to do near field measurements. And we're going to compare the near field measurements of two different boards. They are going to be identical circuits. This is using a 328 micro controller ... a mega 328 microcontroller, here's the micro controller of the peripherals on the two boards are identical. This is a commercial version of the 328, here's the top of the board, here's the bottom of the board. And you can see they have elected to use copper pour. So they did routing on both layers and then everything that wasn't routing they filled with copper and they did it on the top as well, rather than the approach I recommend of signal traces on the top, continuous return plane on the bottom. And someone told them, "Copper pour is just fine. As long as you have some vias connecting between the top and the bottom layers that's good enough." It is an uncontrolled return path configuration. You have no idea if you've got a continuous return path through all these different islands of copper pour here. 

We're going to compare the near field emissions from the bottom of this board with a similar version of this that my students of my class last build. It is an identical circuit. We've got the same micro controller, we got the same interface chip, we got the same crystals everywhere. The only difference is the routing and the layout. This is using signals on the top layer, continuous ground on the bottom, but we do have some crossovers, but we keep those crossunders short. And so it's predominantly a nice solid return path for all of the signal paths. And we're going to use that technique of a 10X probe shorted at the end as our near field pickup, and so here it is. Now I've added on top of the little micro controller board this little shield that's got some LEDs on them and I'm writing the code. The same code is running in both of these. So I can get some current flowing on the board and it's identical code that's running, it's identical I/Os, identical currents that are switching, and I'm using one of the I/Os switching to trigger the scope so that I can look for synchronous emissions when I have all those current switching, either rising edge or falling edge. 

Here is the case where I'm measuring the near field emissions from the bottom of the board for the commercial board, and here it is using the board that my students build, and now here are the measurements. So everything is on the same scale. Here's the I/O that's switching. So we're looking at the falling edge of the I/O in both cases. In the light color trace over here is the voltage noise my 10X probe picks up on the bottom of the board. 

This is the near field emissions from the bottom of the board. Look at that. Here's about 200 millivolts to about 100. It's about 300 millivolt peak to peak voltage noise. I don't know how to translate that into ... It's not going to fail in an EMC test, but you got 300 millivolts of voltage noise I'm picking up in near field from this board just from inductive coupling. It just sounds like a lot of inductive coupling compared to the exact same circuit, different layout. Exactly the same code, exactly the same currents that are running in the I/O. And here is exactly the same probes used to measure the near field from the bottom of my students' boards, and here it is in pink. I don't know about you guys, but I am hard pressed to see any induced noise on the bottom of that board at all. And so if you have no strong compelling reason otherwise, why wouldn't you use a continuous return plane on the bottom of your board in order to reduce the near field emissions from your board? Another example of how layout can affect the pathological noise coming from your board.

Well, we've taken a very quick whirlwind tour. I talked a little bit about crosstalk. I wanted to introduce you to these pathological cases where these problems, these pathological problems will your board to scream like a banshee. We looked at four different examples of them, and we saw in each one of these, how inductance played a really important strong role influencing the amount of pathological noise that we get and how just by changing the layout, just by changing the physical design to engineer sculpt that inductance, we can dramatically reduce the pathological noise. And that is one of the most important takeaways. That if you want to avoid some of these pathological crosstalk problems, it's all about learning to control inductance. 

We looked at the loop inductance in the power path, the shared inductance in the packages, the higher total inductance in the return path of discreet traces rather than nice wide continuous return paths, and we looked at the rated emissions. The mutual inductance between the signal currents and return currents switching in one board compared to the loop in the pickup coil. And it says that if you want to minimize and reduce these pathological sources of noise, you really want to understand the physical basis of inductance. I'm teasing you with this. It's such an important thing. I'll also give you a place to go to get some more information about this. Chapter six of my textbook, Signal and Power Integrity - Simplified. I cover how to build your physical intuition about how the design of the interconnects influence inductance in all of its various forms. And so with that, I'm going to leave you once again with my blatant propaganda and add for other of resources are available for you.

Check out my textbooks. I got two of them from Artech too and from Prentice Hall. I've got a third one I'm just starting now with Artech on best scope measurement practices. You'll be seeing some of that over the next couple years. Be sure to join me on my podcast for Signal Integrity Journal and check out all of our great content on the Signal Integrity Journal website. Be sure to check out the webinars that cover a lot of these topics and how to do these kinds of measurements that I've shown you here in this presentation, and be sure to sign up for your three month complimentary subscription compliments of Teledyne LeCroy to the Signal Integrity Academy. Use that promo code ALT21 when you fill out the form and you'll get your three month subscription. And with that, thank you all very much for your kind attention and happy to answer questions and be participating in the forums over the rest of Altium Live. Thanks so much. Everybody, stay safe. Bye-bye.