Wichtige Aspekte zur Simulation und Optimierung von Hochgeschwindigkeitsschnittstellen – AltiumLive 2022

Die Entwicklung von Leiterplatten mit Multi-Gigabit-Hochgeschwindigkeitsverbindungen erfordert eine sorgfältige Planung. Beim Layout-Routing gibt es zahlreiche Fallstricke, die eine Signalverbindung stören können. In dieser Sitzung beginnen wir mit den Grundlagen der Signalintegrität und sprechen danach über die vielen Designoptionen zur Verbesserung der Signalintegrität bei 16 Gbit/s und höher. 

Insbesondere werden wir uns mit der Widerstandskontrolle von differenziellen Leiterbahnen und den Auswirkungen verschiedener Fertigungsoptionen befassen. Anschließend konzentrieren wir uns auf die Designparameter für differentielle Vias und auf die Optimierung für bestimmte Ziele. Abschließend werfen wir einen Blick auf die Überprüfung von Leiterplattenlayout-Grafiken auf Systemebenenleistung mithilfe von EM-Extraktionstools innerhalb der PathWave-ADS-Toolsuite von Keysight – einer Partnerlösung von Altium Designer. Am Ende dieser Sitzung haben Sie dann ein klares Verständnis davon, wie man mithilfe von Simulationen Designs erstellen kann, die bereits beim ersten Anlauf alle Anforderungen erfüllen.

Keynote-Highlights:

• Wie sich Leiterplatten-Designoptionen bei 16 Gigabit pro Sekunde auf die Signalintegrität auswirken

• Grundlagen der Signalintegrität 

• Bewährte Praktiken zur Widerstandskontrolle 

• Einsatz der Zeitbereichsreflektometrie

• Lambda-Konzept

Weitere Ressourcen:

• Vernetzen Sie sich mit Stephen Slater auf LinkedIn
• Signalintegrität-Ressourcenübersicht
• Signalintegrität-Playlist in der Altium Academy
• Controlled Impedance Routing - Altium Academy

Transkript:

Stephen Slater:

Hello, everyone. My name's Stephen Slater. I'm a product manager at Keysight Technologies, and thank you for joining me today. We're going to be talking about succeeding at 16 gigabits per second. We're going to be looking at how to optimize high speed, digital interfaces. A little bit about myself. I have been a single integrity and power integrity product manager at Keysight for the past eight years. Before that, I was an application engineer for Keysight Technologies in the UK, helping our customers to succeed simulating at some very high frequencies with electromagnetic simulation.

Stephen Slater:

So let's talk about some of the objectives from today's presentation. I've designed the material to be targeted for layout designers, as well as hardware engineers who are interested to know how their PCB design choices are going to affect signal integrity at 16 gigabits per second. So, very specifically, we're going to take a look at an example link, and we're going to vary a bunch design parameters and see what kind of impact they're going to have on the overall signal integrity.

Stephen Slater:

And from that, we should get some intuitive ideas about what control do I have over impedance for transmission lines and Vias. I'd also like to point out that Keysight is a Nexar partner. So that means that what we're going to be talking about today is a workflow where the physical layout design is done in Altium tool set and then brought over to Keysight's advanced design system to do the signal integrity analysis.

Stephen Slater:

Okay, so let's get started. So before we jump in and look at how to improve our signal link, first, we need to touch upon what is signal integrity. Signal integrity is a rather broad topic, not something we can cover in an hour, but what I aim to do is to bring everyone up to a basic level so that we can then progress through into the other sections that lead to the paper today.

Stephen Slater:

All right. So the essence of signal integrity is that we have a transmitter and we have a receiver, a receiver is listening very carefully for whatever signals make its way through the signal path. In our case, the signal path is a printed circuit board with some differential trace routing. And what we want to transmit is digital ones and zeros. And you see this represented as an eye diagram here. If that's something new, don't worry. We'll explain how an eye diagram is constructed in a moment. And essentially what we get at the other side is a closed eye and that's not very good at all. So now can we really tell or discern what is a logic level zero and what is a logic level one? It's not so easy. So although we wanted to send digital signals, what we ended up is looking like a very distorted analog signal at the other side.

Stephen Slater:

Okay. So let's consider we've transmitted this wave form and this wave form consists of bits that are ones and bits that are zeros. And we should think about the unit interval as a measure of time. It's essentially just the duration of one bit. So if we take this wave form and then slice it up, we can slice it up into little windows of two unit intervals each. And then what we could do is we could overlay them together. And if we overlay them together, we build an eye diagram. So, that's essentially what an eye diagram is. It's a way for us to be able to take the entire wave form, stick it on top of itself so that we get a true measure of a figure of merit for exactly how good, how open our signal eye should be.

Stephen Slater:

So on this side, we see that we've transmitted some very nice ones and zeros. On the right hand side, you see that we got anything but ones and zeros. And so the eye on the left hand side, what's being transmitted looks nice and clean, but the eye on the right hand side has pretty much collapsed. Okay. So the most important thing about the eye diagram is what's the eye height and what's the eye width. And do we have a suitable amount of gap right in the center that we can tell what is a one and what is a zero? Okay.

Stephen Slater:

So we're going to go around some of the figures of merit that are important for signal integrity. First up was the eye diagram. We really want an open eye. Second is mixed mode S parameters. Now S parameters are particularly complex. We could use an entire session just to explain and talk about how S parameters work, but for the rest of the presentation today, the way you should think about it is there's one particular S parameter result that we care about the most and that is insertion loss. If we read insertion loss, it basically tells us at some specific frequency, how much signal loss in decibels do we expect to see? So how much attenuation has the signal seen at that frequency? And that's a great way to be able to know how lossy our particular transmission line or our system might be.

Stephen Slater:

The next thing we're going to use as well is called Time Domain Reflectometry. It's basically like sending a signal down a line and waiting for the echo to come back. So by sending a very specific pulse that we have control over and looking at when the pulse returns back to us and how much that pulse has changed when it returns back, we can get an idea about impedance discontinuity, so where impedance changes along the line. And so the most important thing for reading a TDR is that it's going to report to us the impedance that the signal sees and whereabouts it sees it along the signal transmission line.

Stephen Slater:

And then a final figure of merit that's also very important is called the single bit response. We're actually not going to use it in today's presentation, but essentially it's very important for things like being able to see how well the receiver is able to equalize the signal. So this single bit would've started off as a nice digital rectangular sharp edges of this bit. But then once it's been through the channel, you can see that the energy has been delayed and smeared, and the receiver would now need to try and correct for that.

Stephen Slater:

So let's talk about the single integrity workflow a little bit. The physical design would start in our team designer, or if you're a hardware engineer and you don't touch the Altium layout directly, you could use something like Altium 365 to get access to the layout artwork. So you could download the entire PCB release with all of the ODB++ layout files. And then you import the ODB++ layout files into Keysight's pathway of ADS. And then once inside ADS, that's when you would use electromagnetic simulation tools like SIPro or PIPro, so signal integrity professional, or power integrity professional.

Stephen Slater:

These are application focused electromagnetic simulators that take the layout artwork exactly as it is, and then extract electrical models from them. And once you extract a good model, then you can put it back into the analysis schematics, it's the simulation schematic, and then you can run the circuit simulation tools. In this case, I'm showing something that's special for memory. This is a feature set called memory designer inside of ADS.

Stephen Slater:

Okay. So we're going to take a very specific example. This actually forms our example, our nominal design example throughout the rest of the paper. So we start off with a PCB. This PCB is a completed design. It's an evaluation board for FPGA's. And we take a look at one of the traces, which is a differential pair that goes from the FPGA to this connector on this side. So this would be a plugin board that goes into a main board. This one particular differential pair is for PCI Express. We pick up the net and run the analysis. We extract an EM model from one megahertz all the way up to 30 gigahertz, and it takes 51 frequency points. Does it in eight minutes with about 1.4 gig of RAM needed on the machine to do the analysis.

Stephen Slater:

Now for something like SIPro to extract, essentially what we're doing is you're meshing all of these individual pieces and then solving that mesh electromagnetically. We use finite element for the Vias and the transitions. And then for all the planar structures, like the traces, we use a planar EM tool. And so putting these technologies together inside of SIPro means you're able to get really accurate results, but in a practical simulation time. So eight minutes for one signal extraction is really not very long at all.

Stephen Slater:

Okay. So once we've got that model, then what do we do with it? Well, we take the S parameter data, so it's the EM model, and we drop it into our circuit simulation. We set up a generic transmitter and receiver running at 16 gigabit per second, and then we look at the eye diagram. And this tiny little triangle in the middle happens to be the receiver mask. So this is very specific to PCI Express Gen 4, and what we're doing is trying to make sure that as long as the eye stays outside of the mask, then we should be good. We've got design margin to spare. The trace that we extract is about three inches long. And you can see that this design passes without any need for equalization, because the eye is wide open. There's a ton of design margin.

Stephen Slater:

Okay. So now we've got that basis. We understand the workflow. We understand some of the figures of merit. The next thing that we're going to look at is how do we control impedance? Okay. So very first as we're laying out the design artwork, there's often a question about, am I allowed to cross splits in the ground plane? So you could have slots so you can have voids like this. What impact do they have? The most important thing to think about is that our signal travels through the transmission line, but there's also a return current path. And at higher frequencies, the return current path stays right underneath the trace. So it's running in the ground plane directly underneath the trace.

Stephen Slater:

If you're going to put a slot in accidentally, no one's doing it on purpose, but let's say we accidentally route across a slot or a void, then the return current has to run around this cutout. And that adds additional inductance and really destroys our signal link. So you see the insertion loss graph here. You can see the red one is the one we want, that's the nominal case. The slot is not very good, and the void is particularly bad, especially at higher frequencies. Okay. So main takeaway from this is, well, these things should be avoided.

Stephen Slater:

So why does impedance actually matter? So let's stop here for a moment and just consider this on the top line. We've got a transmitter that has a system impedance of 85 ohms. We've got a receiver that has a differential impedance of 85 ohms, and then we've got our signal trace. If everything is matched to the same impedance, then we get maximum power transfer. In this match system, you don't actually get any reflections. So there's no signal reflections and the eye diagram looks pretty good. We've got best signal integrity.

Stephen Slater:

Now, if I do have a section that has a different impedance, so this is a much lower impedance, it's half, and this is a pretty long ... it's a inch section of impedance discontinuity, then we take a look at what it's done to the eye. And you can see how it's actually created this layered effect. And this is because our signals are being reflected backwards and forwards and arriving at the receiver. And so it's significantly decreased the eye height and the eye width. Now in exactly the same setup, so 85 ohms, 42 and a half, and 85, the only thing that's changed on this side is it's a short length, so only 100 mils long.

Stephen Slater:

Now we can see that there's still an effect on the eye, so this eye is not the same as this one. It's definitely reduced in this section, but it didn't have as much of an impact on the eye. And so if there is to be any impedance discontinuities, the shorter they are, the better. That's a key takeaway. All right. So we're going to be designing our strip lines to try to get to a very specific impedance, the system impedance. To know what controls we have over impedance, we need to have an idea about the equivalent circuit model for this. So here, I've got some strip line. You can see I made a little bit transparent above, but there is a ground plane on the top, just like there is on the bottom. The traces themselves, depending on the thickness and the width, it has a certain amount of resistance. And then depending on the length, it will add additional inductance.

Stephen Slater:

There's also a capacitance that goes to ground. And if we take a look at the cross section and we think about the electric field lines, as we see here, we can see that there's going to be capacitance between the signal traces and the ground planes above and below. So the key takeaway from this particular presentation is that the wider the traces, the thicker the metal, we're going to decrease the resistance. If there's a smaller distance to the grounds, if you bring the ground planes closer, then we're going to increase the capacitance of these lines. And if you increase the trace length, then we're going to increase both inductance and capacitance as well. Okay.

Stephen Slater:

So, that's great, but what does it actually do to the signal? Well, let's take a look at the equivalent circuit model. Let's not worry about G. Let's just forget that it's just in there for completeness, but let's consider the equivalent circuit model like this. We've got some resistance, 50 ohms, we've got the inductance and we've got the capacitance to ground. What happens if there's no capacitance and no inductance? Then we would have a perfect transmission line. There's no loss at even really high frequencies. Everything stays at the 50 ohms nominal impedance, but of course, that's not reality. We can't build a strip line that has no capacitance and no inductance. Okay.

Stephen Slater:

So what happens if there was no capacitance, but there was some small amount of inductance? Well, then if you take a look at the frequencies, you see that the insertion loss at higher frequencies, we start to lose our signal energy. And that's because the impedance is increasing at higher frequencies. Okay. If we do exactly the same thing, but this time we say there's no inductance and there's some small arbitrary value of capacitance, then we see that that has a significant impact on loss at the high frequencies. So we have much more attenuation of the signal of high frequencies and that's because the impedance is significantly decreasing.

Stephen Slater:

Okay, so this is really important. It's the most important takeaway of the entire presentation, because we'll come back to this later on, which is that if we were to look at a very fixed frequency and see what happens if we increase inductance, then increasing inductance is going to drive up impedance. Whereas if we increase capacitance, it's going to decrease impedance. And this is the design's challenge. These two things are going in opposite directions, so we have to really try and balance the capacitance and inductance in order to maintain a desired impedance. Okay.

Stephen Slater:

So let's try it out. Here is a strip line example. And we're using a tool that inside of pathway of ADS. It's called controlled impedance line designer and it's an analysis and optimization tool to try to get you the right impedance for these, these traces. Okay. So we put it in as per the nominal design and we look at eight gigahertz. Eight gigahertz happens to be the Nyquist frequency. That's an important frequency for data rate of 16 gigabits per second. So at eight gigahertz, it says the differential impedance is 72 ohms and that's lower than what we want.

Stephen Slater:

So what can we do to increase the impedance? Okay. So since capacitance lowers the impedance, then what we could think about is what if we did the opposite? What if we reduced capacitance? Then we would expect the impedance to go up, right? So we can try that. There's two things we could do to reduce the capacitance. One is we could make these transmission lines to be less wide, so we could make them more narrow. If we make them more narrow, then the capacitance, they're like capacitive plates so they're more narrower, therefore, the capacitance is going to be less.

Stephen Slater:

And then when we re-simulate this, we see that, yep, we can get to 85 ohms, but there's a problem. To get 85 ohms, the trace width becomes 3.5 mil. That's very, very thin, perhaps too thin to manufacture.So we could do it like that, or the other thing we could do is what happens if we increase the substrate dielectric height? And as it turns out, if we were to double the dielectric height from three mils to six mils, then we get to our 85 ohms as well. So both of those are ways of optimizing the transmission line to get to the impedance we want.

Stephen Slater:

So now we've taken a look at that and let's move over and see what control do we have over Via designs? Okay. So firstly, we need to take a tour of the anatomy of a Via so that we're using the same terminology. First, we've got a feed. The feed happens to be our differential transmission lines. The nominal Via design that we had from the PCB was that we had a feed that's coming in as micro strip on the top layer. And then the signal transitions down the signal Vias to an inner layer. And in the case of the nominal Via, it transitioned to almost the bottom layer. So it's called signal layer number five. It's one layer away from the bottom layer.

Stephen Slater:

And then we've got these grounds stitching Vias. Okay, so you can see from view number two that the ground stitching Vias connect through all of the ground layers in order to make sure that the ground planes are stitched together. Both the signal Vias and the ground Vias have pads. Those are like catch pads that we're going to connect into. And then also you can see from view number two and view number three, we've got an anti pad which is like the clearance hole that's goes through all of the plane layers. Okay. So you can think about these signals, these Vias as having capacitance between the plane layers and the signal Via pads themselves, and the signal Vias themselves. Okay. So that's going to be important to recognize that. It's the coupling between the signal Via to those plane layers that adds capacitance.

Stephen Slater:

All right. So let's take a look then at the very first thing we're going to change, which is the drill size. So three cases, six mil drill, which is very small and due to the board thickness may not be actually physically possible to do, and then taking it up to 12 mils drill. And this is changing the diameter of the drill here. So what do you think will happen to the impedance of the Via? Maybe a clue here would be, how do you imagine the resistance to be affected? And then next, what do you think about the capacitance?

Stephen Slater:

So if you thought that a narrower drill would have more resistance, then absolutely, you are correct. And then if you thought that actually the bigger the drill diameter, the closer the outside edge is to the anti-pad, which we can't see visualized here, but the closer it is to the anti pad, therefore, the greater the capacitance. And so that's exactly what happens. And you can see in the insertion loss here that at our frequency of interest, eight gig, actually, the 12 mil drill is much better. It has less loss and significantly more loss in the smaller one, but the 12 mil drill has more capacitance.

Stephen Slater:

So yes, it's got less loss at our frequency of interest, but you can see over at 30 gigahertz, just how much the signal has attenuated.On the impedance graph, you can see that the nominal signal Via actually has quite a high impedance. And so when we add more capacitors, it drives down the impedance, and we can see that the 12 mil drill is getting closer to a nominal 85 ohm design that we want to ... our desired impedance. Okay.

Stephen Slater:

So let's take a look at the next parameter to vary. So what about the anti-pad here? We varied it from the smallest one, which happens to be 37 mils, and then 47 mils, so increasing the anti-pad dimension and then 57 mills. Now, what do you think is going to happen to the impedance of the signal Via? And again, the clue here would be how will capacitance be affected? So if you thought that decreasing the anti pad, so making it smaller, bringing the anti-pad in closer to the signal via, if you thought that would add more capacitance, then you'd be absolutely right.

Stephen Slater:

And so we add more capacitance, and that's going to make the impedance decrease. So you can see that the anti-pad that's got the biggest gap, the biggest separation has the highest impedance. And as we reduce that anti-pad size, the impedance goes down. And so, yeah, so we can see that it has a pretty significant effect on the capacitance and the impedance. This is one of the most important parameters that we have control over.

Stephen Slater:

Okay. Now, another thing that happens in designs is that usually when we do the layout artwork, we use a pad stack. And on the right hand side here, we see the pad stack with all the individual capture pads. And then we route into the ones that we want to. When we come to export the board for manufacturing, we have a choice. We can either remove all of the nonfunctional capture pads, the ones that haven't been used, or we can leave them. Typically, the PCP fabricator has a default choice. They'll either remove them or not, and sometimes it depends on which industry we're talking about. In aerospace defense, they'll leave them alone because the design should be exactly as determined.

Stephen Slater:

So what do you think is going to happen to the impedance of the Via if I have all these capture pads in place? Well, if you thought that having all the pads in place would add to the capacitance, then you're absolutely right, because there's many more of these plates. There's much more capacitance with no pads. We see the impedance. And then with the nonfunctional pads, we see the impedance drops significantly. At the same time, you see that at the higher frequencies, this extra capacitance is really hurting us. And we have a lot of loss at the high frequencies, but at our frequency of interest, actually, the case with the pads is better. So right here, it's looking better. And that's because right now our impedance is too high and adding the capacitance is making it closer to our desired impedance.

Stephen Slater:

All right, let's move now onto stitching Via placement. So here you can see we've got 30 mils to the stitching Via. That's the closest, okay. The way you should think about this is our signals are traveling through the signal Vias, but then what about the return current path, the return currents flowing through the ground planes? And the further away the stitching Via is to those signal views, the longer the path that you're making that return current travel. Okay. So, therefore, it's going to add additional inductance, so let's maybe see how this is going to affect our overall signal loss.

Stephen Slater:

Okay. So the closer that we bring the stitching Vias into our signal Vias, that's going to give us reduced inductance, so that's great. If we add more stitching Vias, where the final case where there's four Vias, then that also gives us less inductance. But as you can see on the impedance chart, it doesn't really have a huge impact. Okay. So it's the 30 mils case, the 37 and a half. You can see that these have the higher impedances, whereas the 45 mil case, that has less inductance, therefore the impedance is going to be a little bit lower. Okay. And effectively it's not so easy to see right here, but what effectively is happening is that the inductor, L, and the capacitor, C, they work together to form a low pass filter. And so this is why balancing the L on the C so very carefully is what helps us to try to design for a better interconnect that has less loss across a wider frequency band.

Stephen Slater:

All right. So let's now move on to layer choice and back drilling. Okay. So the normal design look like this. We come in through the layers that are on the very, very top. And then we transition down to signal layer five, which ... it's the lower most signal layer that's internal to the structure. So not the bottom, but it's nearly optimal because it comes in as far as it can. It's strip line and it leaves a very short amount of stub. The one in the middle happens to be a bad design choice, because we come in from the top layer, we transition to the first internal layer, and that leaves a really long signal stub.

Stephen Slater:

Now that would be okay if we could back drill. So back drilling is where they actually just take a drill bit and they drill from the bottom side and remove the excess stub. And in a moment, we're going to see how the bad layer choice versus the back drilled, what kind of impact they have on the signal. But before we do that, it's not obvious why a stub is bad at all. I think we know from design rules that we shouldn't leave stubs, but let's go and examine a little bit, the theory behind why stubs are bad.

Stephen Slater:

Okay. So if we jump in and just analyze the stub of a differential via, it's got a certain amount of length, let's say 75 mils, like this. And the thing is, is that as our signal travels through the Via, the voltage varies as a function of the length, okay, because this is electrically large. And so the signal travels down the stub, hits the bottom and then reflects back. So this is like a two dimensional view of what it would look like. The sum of the signal goes straight through to our output trace like we wanted and that's what we see here, so we've got a nice signal transitioning through. And then some of the signal goes down the stub, gets reflected and comes back.

Stephen Slater:

And here we introduce the concept of Lambda, which is the wavelength of signal that's being transmitted. Okay. So let's say a quarter of lambda, it means that the signal travels down one quarter of the wavelength, and then one quarter back. That's a delay of half the wavelength. And you can see that the signal comes back in and, oh, dear, it's now out of phase with the original signal that was sent. Okay. So the signal goes down and back up, and then it cancels. And that's the problem. So the signals are equal and opposite, they cancel each other out, and we call this a quarter-wave stub resonance.

Stephen Slater:

So at this very specific frequency where the wavelength happens to perfectly match this lambda on four, it appears as though no signal is getting through. Based upon the length of a stub, we could actually work out where we would expect this resonance to be. So we don't really need to follow along with the math, but we can just say that we know the speed at which signals travel through signal traces. So for a PCB substrate, like Fr4, it travels about six inches per nanosecond. We know the length of this stub here and so we can calculate where the resonance is going to pop in.

Stephen Slater:

Okay. So that explains why we have a resonance. Now let's come back to this and let's take a look at what the actual impact of the signal's going to be. All right. So with a long stub, do we get a resonance? Yes, we do. And it drops down at about 24 gigahertz in this case. If we were then to back drill those stubs, get rid of them. Okay, so that's what the yellow represents. It's just where the drill bit has been, so it left as an open void. Then we can see that now the insertion loss is much flatter to a much higher bandwidth. And in the impedance chart here, you can see the difference.I think impedance is a little bit more difficult to read for the case stubs versus back drilled. The most important figure of merit here at the moment is going to be the insertion loss. You can definitely see that there's no resonance in the back drilled case. Okay.

Stephen Slater:

All right. So we've taken a look at signals in transmission lines. We've taken a look at Vias. Now we come onto some of the topics, like what about surface roughness? What about crosstalk? And what about intra-pair skew? All right. Surface roughness, two things to think about. Number one, there's a physical phenomena called skin depth. And it means that the higher the frequency, the more the current crowds to the outside surface of the conductor. Okay. So it starts, although the current density now is confined to that outside skin of the conductor. If you think about, well, what about a DC? A DC, no, the entire conductor is being utilized, but the higher the frequency of the signal, the less of current that's actually traveling in the center and the more current traveling on the outside.

Stephen Slater:

So you consider that and then consider that we've got a two dimensional cross section of our conductor. And we see that the outside edge is a bit fuzzy and it's a bit fuzzy because it's not perfectly smooth. The copper has a roughness. As a designer picking the substrate stack up, you get to pay extra money for smoother copper if you choose to. And for some really high speed signal traces, you might need to do that, but we can actually use the same controlled impedance line designer tool that was inside ADS to verify how much of an impact surface roughness have so we can quantify it.

Stephen Slater:

Now, I want to analyze it, let's say both sides, like really rough case, and then perfectly ideally smooth. Let's just try and quantify the difference that surface roughness has. So the really rough case is eight microns. It's called RZ, but it's pretty much the height of the RMS value of the peaks on the surface. And across a three inch trace, we can see that there's 4.6 DBs of loss at eight gigahertz. But if I compare that to the ideal case where it's perfectly flat, perfectly smooth copper, there's only 1.9 DB of loss. So surface roughness gave us an extra 2.7DB of loss at eight gig for this three inch trace.

Stephen Slater:

And an important thing is that the amount of loss is going to depend on a couple of things. One, the roughness of the material itself, two is the length of the line. So the longer the trace, the more the roughness is going to play a part. And three, the frequency at which we're looking. So the higher the data rate, the more surface roughness is going to have an impact. Okay. But the takeaway is it's significant. At 16 gigabits per second, we need to take surface roughness into account.

Stephen Slater:

All right. Let's now take a look at crosstalk. Okay. So this is the beauty of simulation is that we can set up our circuit simulation however we want. So up until now, we've just been looking at a pure transmitter and receiver, but what if we add in crosstalk aggressors? These are the near neighbor signals to our signal of interest. And we turn on crosstalk and we have full control, so we can make an incredibly tight coupling between them. I reduced the spacing between these transmission line down to five mil mils, just to make sure that we get maximum amount of crosstalk. And what'd you expect? Well, I was rather disappointed, really. I wanted the crosstalk to really destroy the signal, but as you can see, there is an impact to the eye, but not incredibly so.

Stephen Slater:

And that's because a very important takeaway of this is that strip line itself is rather impervious to coupling. So we don't really need to worry so much about our signal phrases. If they're routed in strip line, the crosstalk between them is going to be minimal. We do know that the longer those differential pairs ... Well, actually, sorry. One thing is that differential themselves are more impervious to coupling than just the single-ended signals would be. The second thing is the strip line is much better than micro strip for reducing the coupling between them. We do know that the longer the traces go, the coupling will increase. The higher the frequency, the coupling will increase. But the final thing is that crosstalk in the Vias is something that we really want to be able to take care of and to analyze. That's something I wish I had done, but I didn't get ready for this paper, so that's something I can take away as an extension item for later.

Stephen Slater:

All right. Let's then talk about intra-pair skew. So as you route differential pairs, you can never just go straight to where you need to go to. You always need to turn a corner, and whenever you turn a corner, one of the traces takes a shorter path than the other one. So when you turn a corner, whichever one's on the outside is going to be going through a longer signal path than the inside one. So by the time we get to where we're going to, you'll find that one of those signal traces is much longer than the other. And that's not great because we really want to make sure that these signals to individual traces are equal length electrically. So to compensate for this, I'm sure that everyone feels comfortable. We add in these serpentines, a meander that adds additional length to whichever trace happened to be the shorter one.

Stephen Slater:

But how close do you need to get in order to keep the signal integrity looking really well? Well, surprisingly, you can see from these couple of eye diagrams, the very first one shows no skew. The next one to the right shows 15 picoseconds of skew, which happens to be about 80 mils of difference in length between the signals. You can see the eye diagrams nearly look the same. There definitely is some difference, but they nearly look the same. If I go to 30 picoseconds of skew, then my signal's looking particularly bad. And of course, if I go to six picoseconds of skew, there's no eye at all.

Stephen Slater:

So how close do we need to keep this intra-pair skew under control? The way I like to think about it is consider the skew as a proportion of the unit interval. So to work out what the unit interval is, we've got our data rate, okay, at 16 gigabits per second. So the unit interval is 1/16e9. That's 62.5, E minus 12, which is 62.5 picoseconds. Okay. So of course, when my skew is 60 picoseconds, of course, I'm completely out of phase. The two signals are completely out of phase with each other.

Stephen Slater:

When they're only 15 picoseconds, then I am just a percentage out of phase between my two signals, so I still get a reasonable eye. And so the key takeaway is that skew definitely does matter. Consider how tight your routing needs to be, how tight you need to match it based upon ... oftentimes as design standards that come. So for PCI Express, they'll give you usually some routing advice as to how close they need to be. But the other thing is don't go chasing down to the last 10 mils. You can see that this is 80 mils difference at 16 gigabit per second, and the eyes nearly look the same, so, yeah. Okay.

Stephen Slater:

All right. So now we're coming to the end of the presentation. We've covered a lot of ground though. There's a lot of takeaways. Just want to recap very quickly some of the things that we learned. So first, slots and voids are bad, avoid them. Second, we need to design towards a system impedance and try to match the impedance all the way through. There will be discontinuities and impedance, but if they're electrically short, that's not too bad. We saw that with the back drilled Via. There is a discontinuity, but it's not as bad as if we had a much electrically longer one.

Stephen Slater:

If we observe the loss at a fixed high frequency, then increasing inductance is going to increase the impedance. So inductance increases impedance, capacitance decreases impedance and we have to try to balance both out. If we can keep them balanced, then that's perfect. Ideally, if we can minimize both, then that's going to give us the highest bandwidth of operation, but therein lies the design difficulties. We're always physically constrained. When we come to the Vias themselves, a bigger drill is going to give us more capacitance. A fixed drill with a smaller anti-pad size is going to give us more capacitance, nonfunctional pads will give us more capacitance.

Stephen Slater:

Those stitching vs have most control over the inductance. So if the closer you can move them in, the less inductance there will be. More stitches means we'll have lower inductance, but sometimes it's just not worth it. Well, stubs are bad. We probably knew that coming into it, but at least we've explained why and the choices that we've got. Something we didn't mention was that the choice of lasered micro Vias definitely look really good, so that's a really good choice. That's an alternative to back drilling Vias. Surface roughness is a problem for 16 gigabit per second. We need to take that into account when we're analyzed.

Stephen Slater:

When it comes to crosstalk, don't worry about the contribution of crosstalk and strip lines so much. We didn't see it, but I would've liked to have shown you what crosstalk in the Via arrays would look like. And that's something where we are going to be careful about crosstalk.And then finally about intra-pair skew. You have to think about it as a proportion of the bit period, try to match those differential trace lengths to a reasonable level.

Stephen Slater:

All right. So that much covers everything that we've captured today, but I've got one more bonus item for you, which is what if we take what we know about the control we have over impedance for traces and the control we have over impedance for the Vias? And what if we try to do a better job of matching everything? So, that's to what I did. I started with a nominal design and then using the Via design tool in ADS, I optimized some of the parameters to try to get to something that was closer to 85. There's still room for improvement there, but I definitely got it closer. It's something down around, say 83 ohms. I optimized the impedance of each of the transmission line sections to 85 ohms, so we've nearly got a perfectly matched system.

Stephen Slater:

What did that buy me? Well, look at the nominal design. We had pretty good eye height already. And now with the optimized Vias and traces, there's an additional 50 millivolts of eye height and 0.6 picoseconds in eye width. That's actually huge. 50 millivolts in eye height is a lot. So I'm really happy that the optimization showed a great improvement, but we would also point out that, Hey, there was great design margin anyway, the existing design was very good. Did we need to do the optimization? In this case, perhaps not, but if design margin was tight, we know that we have full control over the Vias, the Via design, the trace design in order to get what we need to get to. And then finally the receiver themself can turn on equalization and that can open up the eye even more when we are at the limit. All right. So now we've come to the end of the paper and I think it's a great time to now transition over into our question and answer session.