About Author

John Medina

With over 30 years of extensive experience in PCB and Package design,
training and Signal integrity analysis using state of the art tool sets,
including Expedition, CES (Constraint Editor System), Altium, Hyperlynx,
Interconnectix (ICX), Power SI,  Boardstation RE/XE and Allegro v16.x
including CMS (Constraint Management System).
John has expertise in complex PCB designs, and delivering training of PCB design tools and methodologies, including: HDI, high speed, RF, mobile wireless products, mixed technology designs, signal and power integrity verification and analysis
using Hyperlynx tool suite, and Hyperlinx DRC.
John has worked at Northrop Grumman completing PCB designs for Aerospace
and Military products and has previously worked for Apple, HP, Agilent, Nokia and
Cisco and built teams that deliver complex HDI CPU designs. He has also implemented a PCB Process and tool flows, which includes SI Tools for verification and worked at Intel doing Package Flip-Chip design for server team.
Recently John worked for Mentor Graphics as a Field Application Engineer. He supported Qualcomm, Northrop Grumman and Intel providing expertise and training for
Package/PCB co-design utilizing Xpedition Package Integrator. He has experience with Calibre LVS DRC. John also has a pending patent on Bump Compensation methodology.