DDR4 Evolves Memory Bandwidth for Computing Power

Double data rate (DDR) memory is an integrated circuit used to store and retrieve information. It is used by central processing units and their chipsets within embedded systems. The ICs are synchronous dynamic random access memory (SDRAM) technology. DDR memory is used as a digital filing system, serving as a repository where data is stored and retrieved for computing operations. A CPU must have memory ICs to place the instructional sets of programs, such as operating systems.

Memory ICs discussed in this article are called double data rate because the memory transfers data on both the rising and the falling edge of the IO bus clock. Two bits of data are processed for every clock cycle. Ability to process two bits of data for every clock cycle results in greater bandwidths to move data at faster computing speeds. With 64 dedicated pins in parallel groupings, trillions of bits are processed before your next keystroke. It is a digital work of art!

DDR memory has continued to evolve along with CPU chipsets to allow faster computing power. There are now four generations of DDR memory: DDR, DDR2, DDR3, and DDR4. Plans to release DDR5 are in the works with targeted delivery dates some time in the year 2020. Each generation of DDR memory have standards developed by the Joint Electron Device Engineering Council (JEDEC). Council representatives work together with industry developers and chipset vendors to define the standard.

Defining Characteristics of DDR Memory Chip Generations

Faster data transmission has been possible because of continued material evolution. Process houses are able to continually shrink the die allowing more gates operating at lower voltages. More gates allows more bits for storage and retrieval. Increased access to bits for processing does lead to increased temperatures from power consumption dissipated across the die.

Memory chips are installed on every motherboard

Material evolution allowed discovery of new architectures that increased computing bandwidth while managing temperatures within the memory chips. Tradeoffs discovered and implemented architecture that include faster IO bus clock speeds while maintaining slower internal memory clocking. The combination of IO bus to memory bus created a ratio that doubles or quadruples transfer rate of information to and from the CPU.

Bandwidth: This is the DDR peak transfer capacity, in MHz.

Chipset: A set of electronic components in an integrated circuit that manages the data flow between the processor, memory, and peripherals.

DIMM: Dual in-line memory. A module that contains one or several random access memory (RAM) chips on a small circuit board with pins that connect it to the computer motherboard.

DDR: Double data rate. A computer bus that transfers data on both the rising and falling edges of the clock signal.

Memory Bandwidth: The maximum throughput of memory, in MHz.

Memory Latency: The time between initiating a request for a byte or word in memory until it is retrieved by a processor.

Memory Timings: This describes the performance of synchronous dynamic random-access memory (SDRAM) using four parameters (in units of clock cycles):

CL: Column Address Strobe (CAS) latency. The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must be agreed on between the memory controller and the memory.

TRCD: Row Address to Column Address Delay. The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL

TRP: Row Precharge Time. The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL

TRAS: Row Active Time. The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2^CL. These parameters specify the latencies (time delays that affect speed of random access memory. Lower numbers usually imply faster performance.

SDRAM: Synchronous dynamic random access memory. Memory with an interface synchronous with the system bus carrying data between the CPU and the memory controller hub.

Transfer rate: The number of bit transfer made from memory during one cycle of the IO bus clock. Given as: (IO bus clock rate) * 2(for dual cycle) * (I/O bus clock/Memory clock)

Considerations When Choosing from DDR Offerings

Take advantage of higher bandwidths by choosing DDR memory sticks that maximize computing power for your CPU chipset. For DDR, the IO and memory bus are equal. For DDR2, the IO bus is twice as fast as the memory bus. For DDR3 and DDR4, the IO bus is four times as fast as the memory bus.

Building bandwidth over DDR generations

Taking a look at the relationship of chipset IO clock to internal memory clock produces bit transfer rate. With transfer rate, maximum memory bandwidth for access may be determined. Transfer rate is calculated as follows:

Transfer rate (MT/s) = (memory clock) * ( 2*IO clockMemory clock)

Memory bandwidth is found as follows:

Memory bandwidth (MHz) = (transfer rate) * (bus width in bytes)

DDR2, DDR3, and DDR4 transfer 64 bits and may be organized into banks for maximization of transfer. Customization into banks allows development choices alongside the CPU chipset and its design features. Use your chipsets design features to choose complimentary memory following JEDEC naming standards. The JEDEC standard naming convention is defined as follows:

DDRz-xxx, PCz-yyyy Where, xxx = Memory clock + IO clock yyyy = Memory bandwidth z = Memory generation, i.e. variant 2, 3, 4, or 5

The following parts include one representative from each DDR category. Navigating to our website from the part link, below, with point you to its page. There you will find sourcing and pricing information. In addition, at the bottom of the same page, our website lists parts with similar specs to facilitate comparison shopping when selecting memory.

Corsair Vengeance LED DDR4

This is top-of-the-line memory, Corsair Vengeance LED DDR4, for gaming enthusiasts or other users with need for color coordination to complement chipset operation. It includes an RGB light bar for custom lighting. Heat management for this high-functioning memory stick is supplied with built-in heat spreaders.

Found on www.corsair.com/us/en/VengeanceLED

Kingston, KVR16N11S8H/4 DDR3

This is DDR3 memory offered by Kingston, the KVR16N11S8H/4. It is intended for use in desktop PCs and its maximum bandwidth is 12.8GHz.

Found on page 2 of Kingston [KVR16N11S8/4]

Kingston, KVR800D2N6/2G DDR2

This is DDR2 memory offered by Kingston, the KVR800D2N6/2G. It accommodates maximum bandwidth of 6.4GHz.

Found on page 1 of Kingston [KVR800D2N6/2G]

Micron, DDR SDRAM, MT46V32M16P-5B

This is the oldest type of DDR still available on the market. It is offered by Micron under part number MT46V32M16P-5B It is used in legacy applications although it could be chosen for architectures without need for higher memory bandwidth. Several speed grades are available, as shown in the table below:

Found on page 2 of Micron Double Data Rate (DDR) SDRAM MT46V32M16P-5B datasheet

DDR memory is available in many configurations to maximize bandwidth for computing power. Using DDR with maximized bandwidths requires chipsets that support memory architecture per JEDEC standards. Take a look at our parts finder when you next need to choose memory. Using our parts finder will maximize your selection process with powerful computing tools.

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