Why Protect Vias and What is IPC 4761?

Judy Warner
|  Created: March 18, 2019  |  Updated: February 5, 2021

Why do we need to protect vias? Here to answer is Gerry Partida, Director of Engineering at Summit Interconnect Technologies. Summit is an advanced technology manufacturer creating custom printed circuit boards. Summit focuses on complex rigid and rigid-flex products and offers extensive expertise in RF/Microwave applications. In today’s episode, Gerry will help us untangle IPC 4761 and get actionable info that you can apply to your designs.

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Show Highlights:

  • IPC 4761 comprises design guidelines on seven existing methods of via protection
  • Combinations: Capping one side vs the other side, dry film soldermask with soldermask over, or via plugged with solder mask capped over with soldermask or not, plated shut via epoxy filled and plated over, or via and pad also known as Type 7 which is popular for HDI (High Density Interconnect)
  • Why protect Vias? To prevent solder paste from running down an open via to the other side of the board, preventing solder balls on the secondary side, moisture protection, sealing to prevent chemistry entering and becoming trapped, to ease the subsequent processes, and finally assembly
  • For via protection with a surface finish like ENIG or ENEPIG, both sides of the via need to be open during the ENIG or ENEPIG process.
  • IPC 6012 Class 3 now prescribes the same thickness for copper wrap plating
  • Why do people fill? Primary reason is to get the via at the pad connection in the component
  • When you’re talking about High Speed Digital, you don’t want to go from trace to via
  • Place via in land to avoid delay and reduced real estate for routing
  • Slight reduction in reliability when via is plated, epoxy-filled and plated over versus a via only plated in the final
  • Peel strength is much lower when you epoxy-fill is in the center and plated over
  • You have to buy IPC standards
  • Encroach soldermask clearances - encroaching soldermask on top of the LAN but not in the hole is an excellent solution.

Links and Resources:

Summit Interconnect 
IPC standards 
IPC on Via Protection


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Host: Judy Warner
Guest: Gerry Partida
J: Hi, everyone it's Judy. Welcome back to the OnTrack Podcast. Have you ever wondered about the best way to protect your vias? As promised in an earlier podcast, we've brought in a manufacturing expert, who is Gerry Partida, the Director of Engineering from Summit Interconnect Technologies. He's going to tell you the seven ways to protect your vias and really untangle IPC4761. So lean in, enjoy and I'll see you on the other side.

Judy Voice Over: Welcome to Altium’s OnTrack Podcast where we talk to leaders about PCB design, tackling subjects ranging from schematic capture all the way to the manufacturing floor. I'm your host, Judy Warner. Please listen in every week and subscribe on iTunes, Stitcher, and all your favorite podcast apps. And be sure to check out the show notes at Altium.com/podcast where you can find great resources and multiple ways to connect with us on social media. 

Judy Warner: Thank you so much, Gerry, for joining us today. We're so glad you could join us and share some of your wisdom from inside a board shop about vias.

Gerry Partida: I appreciate the opportunity to share the knowledge to help our end users have boards with no issues.

J: Yes. Wouldn't that be lovely? That's what we all shoot for, right? So one of our listeners, Jesus Castanani, I believe it is. Jesus, so sorry if I butchered your name, but Jesus wrote to us asking us specifically about via protection. And I know there's a lot of ways to skin that cat. So can you tell us a little bit - first of all, let's just start with the obvious one - why protect vias?

G: This is an excellent question, and there are decisions that designers can make that will impact cost and delivery, and sometimes it doesn't make sense why we have certain types of via protection, but I'll kind of go down the list. The document IPC4761 covers the design guidelines for via protection. And most of them are talking about coverage, whether you’re capping on one side or the other with liquid photo imageable solder mask; which they don't recommend as a cap to make it sealed. Although it does work most of the time with a smaller end via and a high aspect ratio, and then they also have dry film solder mask coverage, which is not common but it is used and it has certain applications for it. And then there are combinations of capping one side versus the other side - it’s not a good idea to cap with solder mask on one side and we'll discuss that, and then you can have both dry film solder mask with solder mask over or a via plugged with solder mask and capped over with solder mask or not. We have both designs that we built for our customers, and the last one where you take a via, you plate it shut, you epoxy fill it and plate it over, and you can do via in pad, which is a type seven, and is very popular these days for high density interconnect. But there are considerations to take for wrap plating and the amount of copper it builds up on a layer that requires epoxy filling.

J: Now all of this is basically to protect the via or enable HDI, but also affects solderability issues when it gets to assembly.

G: Right. So, sometimes the protection is to prevent solder paste from going down a via that's open to the other side of the board and causing defects or solder inside, and the second when they do the secondary side, what will that solder do? Will it cause a solder ball as the moisture builds and explodes it out? Sometimes, and I've seen actual pictures, where they use dry film solder mask on one side of the board because the board is so hot on one side they’re blasted with cold air and it actually causes condensation, and ice builds up on the board.

J: Wow.

G: We don't want any moisture to go through the board, so that's like a level of protection that's extremely high. There are times when they want to seal it so that there's no chemistry leaking in there and getting trapped. So, that's another type of protection from processes that we will do following on, as well as in assembly. When it comes to the via protection with a surface finish like ENIG, you cannot have one side covered in a via and the other side open. As we process ENIG, we have to have both ends of the hole open and what happens if you cover one side - the first thing you do is micro etch, then prepare the surface. The next thing is you palladium seed. The problem is, the micro etch is now stuck in this cave, where it's capped on one side and we can rant as much as we want, but you sometimes don't get it at the back end of the hole.

J: Does it create a vacuum?

G: No, what happens is it stops the palladium. Nickel does not go directly to copper, it goes to palladium.

J: Right.

G: So you have the palladium, seed the surfaces of the outer layer. But if you have a via that was capped one side and there's some micro-etch, it’ll leech out in the bath and prevent palladium from seeding on your surface mount lands, then you don't get any nickel...

J: Oh, interesting.

G: -and you have a dark pad. So, we have to have both sides of those holes open. If you do solder mask over bare copper and call out ENIG, we have to open the side that you cover with mask, even though we put solder mask everywhere, we leave it open, we do ENIG, and then we have to do an additional imaging, develop, screening and curing solder mask and it adds these extra process steps and time to build your board. And then you have to worry about is the via too close to a land, that when we cap this, we don't bleed onto the surface mount land. So, these are things to take into consideration, that when you do certain surface finishes–even covered both sides–we actually open both sides for ENIG, no matter what.

J: Yeah, that makes sense. It seems like I remember, at least back in the day, it was practice where we put a dry film over. It could cause a blowhole and the heat would build up and blow the mask out at assembly if you trap moisture. So I mean, it seems like these days, though, a lot of people are filling with conductive epoxy and capping.

G: On non-conductive primarily.

J: Oh, non-conductive, sorry. Yeah, so conductive has sort of gone, by the way correct?

G: Yeah and I can share some of the reasons why. 

J: Okay, so why don't we just jump in.

G: So, when we do what's in the IPC document, which is type seven, which is we're going to plate the hole, we're going to epoxy fill it, and then we're going to plate over it. There's a requirement that when we place copper in the barrel, that's going to be epoxy filled, that the copper wraps onto the surface of the outer layer. IPC6012, class 3 and 2 now, has the same thickness. You have to put copper onto the surface, a minimum of two-tenths of a mil on top of the starting copper. So if your copper was half an ounce, seven-tenths, you now have to have a minimum of an additional two tenths on the outer layer, so it has a plate on the outer layer to the top - it's called wrap plating - the target is two-tenths of a mil. My hair is two mils thick, we’re trying to target something that's one-tenth of my hair thickness, and it's a very particular process. But we don't target the minimum. We actually go slightly beyond the minimum because later on, we're going to planarize the surface. So when we do type seven, we do wrap plating, put enough copper in the hole and wrap the surface, and then we stop. So if we want two tenths, we target four to six tenths, but we still don't have enough copper in the hole. We probably only have about three tenths to about five-tenths of copper in the hole. So then we stop, we cover the entire surface of the panel, except for the vias that are going to be filled, and we have an opening slightly bigger than the drill, and we plate copper in the hole, to the correct amount of copper thickness that we want in the barrel per your procurement document. Then, when it's done, we pull off the resist film, and only plate in the hole, a little button - a little dot - around the hole. The rest of the surface is the original copper plus wrap plating on both sides. Then after we plate enough copper in the hole, we're going to epoxy fill in the hole to fill it, we’ll cure it, then we'll sand it - these little buttons that we created - we can't have them. We want to live in a two-dimensional world when we're imaging. So we sand off the little buttons we created on both sides. And then we go back and verify that we still have the two tenths minimum wrap required from in the hole onto the starting copper. And if it's gone beyond it, it goes into scrap. So this whole process of adding plating and epoxy filling vias, is typically about eight basic manufacturing steps, and it takes a minimum of a one day to process - typically it’s going to be about two-day process - in production it’s more like three days, but you're incurring probably 20 to 25% more cost to plate, epoxy-fill and plate over your board, so if you need it, just understand it's going to take a longer build cycle, and it will definitely add cost to the board and the design. 

J: Why do people choose to fill?

G: The primary reason is to get the via at the pad connection, in the component. So when you're talking about high-speed digital, you don't want to go to a trace to a via, because that is all delay. By putting the via in the land, there is no delay to get into the signal.

J: I see - it's a performance issue.

G: It's a performance issue. The other thing is that it reduces the real estate that opens up for routing. So you get more routing channels as well. There is slightly lower reliability in a via that is plated, epoxy filled and plated over, versus a via that's just plated in the final. And the reason for that is, there's a different TG and thermal expansion of the epoxy from the copper barrel and from the laminate. So you have three different movements that are different than just a plated hole that's got air, or maybe cap and solder mask. And if you do reliability tests like PCQR squared from conductor analysis technology, which we've done multiple tests over a decade, you can see a slightly different cycle, longevity between a through-hole, not epoxy filled, and one epoxy filled. They will still meet all the requirements of IPC, but there is a slight reduction in reliability when you plate,  epoxy fill and plate over. So just understand that. Another thing that you're trading off is copper foil when laminated to make a printed circuit board has the peel strength - sometimes about six to nine pounds per square inch peel strength, which is really good for assembly. It survives very well. However, when you epoxy fill, you have the peel strength around where you drilled - you still have it, but where the epoxy is filled in the center, and we plate over it, that peel strength of the epoxy, is probably about two pounds per square inch. It's much lower.

J: Is that because epoxy is somehow slick?

G: You’ve planarized it, which is a fancy word for sanding. So, now you would polish the surface, and then you deposit electroless copper that has no way to dig into it, so it has very low peel strength, and then you plated it on top of it. So, if you do too much heat or too much rework over a via in pad with epoxy fill, you may see, a bubble, I don't see it too often, but occasionally you do.

J: So, you're seeing boards day in, day out. Like you said, it's always a trade-off, right? It's what are you trying to accomplish, what are the tradeoffs, costs, reliability; all these things come into play. Through Summit, do you see more filling, or do you just see across the board a variety of things? In other words, is there a trend?

G: The trend is to do more and more epoxy filling it is more and more common. It does help with giving you routing channels on outer layers where you would have had a land, a traditional trace and then a via. Well, if it's inside, that's a channel to ameliorate traces, so it gives you rating rounding channels and then speed performance. Once you have the via in the land, you're right to the component, you don't have a delay. It's a big reason for this being used,  but you have to consider that when you add the wrap plating, the feature spacing is harder for manufacture because our ability to make space is all based on what is the total copper I'm trying to etch through? Not the finished copper thickness that we’ll plate up, but the base copper, which was the original copper plus wrap plating. And if you have a blind via, let's say we have a ten-layer or twelve-layer; a one-to-six - that requires wrap. And then you have a one-to-twelve with epoxy fill; that's a secondary wrap on top of the first wrap. And so you can make your base copper thicker and thicker and thicker and it's harder to make the finer features, which is why you were trying to do a high density interconnect in the first place.

J: Yeah, I've seen this. Again, I think as designers - not being manufacturers - you don't calculate in that additional plating when you go into the sequential land or whatever, you don't realize: oh, it's going through this three times, and you're adding little bits of copper each time, and I remember when we were in RFM Microwave, we'd be like: Wait, I ran simulations why is it doing this? I'm like: because there's way more copper. Then: but why? I'm like, well, you have to learn to be a board manufacturer to answer that question. So I think that's a very commonplace area. 

G: And in the finished product, on epoxy-filled vias is there's an allowance of a two mil protrusion up or a dimple in the hole of two to three mil.

J: Yeah, let's talk about that. What does that do? Because I know, and I think that the machinery's gotten better for the planarizing?

G: Yes, it has gotten better, but again, we have to go look at the geometries of the design that we receive. I have a customer that has a 150 mil thick board, and they want to use a 10 mil drill, and the aspect ratio was 15:1. There's no way we're going to fill the epoxy from top to bottom. IPC requires a 60% fill from top to bottom, and it's like there's no way I can do it with 150 mils thick, and I should be drilling 16, 13.5 maybe, but I will lose a panel here and there where I'm violating the 60% fill.

J: A panel that you're going to lose here and there, but you're going to still charge the customer for it because that's not free.

G: Right, your pain for the risk that we're taking...

J: -is a yield issue, right? So, and you could do that, and sometimes it's worth the risk to do that.

G: So this takes us to the question of the conductive and non-conductive epoxy fills. The non-conductive is not as thick, and we can fill the epoxy in the vias much easier with non-conductive epoxy, than the conductive epoxy.

J: Oh, that's why.

G: The other problem, too, with the conductive epoxies, is they are really thick, so you can't get the same aspect ratio. They don't really gain you anything as conductive, and there are two different types of conductivity. There's thermal conductivity, and then there's electrical conductivity. But the difference, it may use copper or other metals in the epoxy when they fill it, but the resistance is still so high in the epoxy, the copper plating in the barrel’s carrying all of the signals and all the current.

J: So the barrel’s doing the heavy lifting?

G: Oh, it’s doing all the lifting because it’s the lowest path of resistance by far, and so it just goes. And so some people go, well, I want to conduct heat from one side of the board to the other. I want to use conductive epoxy. Well, the thermal conductivity of the best conductive epoxy is sixteen. Where copper I think is 346 or 326. So, what I tell the customers; instead of plating one mil of copper in the hole, plate 2 mils of copper in the hole and then calculate how much conductivity you have versus an epoxy fill of 16, and they’ll come back; oh yeah, I will go with 2 mil in the hole. Just make sure that because we've lost 2 mils of the diameters filled by copper, to fill that, we want to make the hole big enough so that we can put 2 mils of copper plating and then still epoxy fill.

J: So you need a bigger drill, obviously there.

G: And it's not that hard to do the two mils of plating in the hole because all your plating over those vias, which will be epoxy filled, you're not really adding it to the surface of the board, you're just putting it in the barrel of the hole.

J: I see. Because everything is masked off at that point, right?

G: Yeah, and it's a really good solution for conducting heat from one side of the board to the other.

J: Interesting. I was going to ask you about thermal because I'm imagining that that would be a desire. right? 

G: Yeah, the only reason they have epoxy-filled holes is they have, like a QFP and a ground in the center to draw heat. And they have vias and you want to draw the heat to the other side to dissipate. So the best bet is just plating it with more copper in the hole, it will conduct more heat.

J: Interesting. That's why we had you here, Gerry. Smart guy. So we've talked about some sort of hazards of doing it badly. Tell us a few more of those; like if you do this then this, or tell us, maybe some war stories where it can go bad if you don't do it properly?

G: When we try to epoxy fill a really high aspect ratio. There are times where we can't fill the type you see, which is 60% fill, but we can make the outside flat and flush. So then there's a condition that we're agreeing between a user and a supplier that we're not going to need IPC fill, but we'll make sure it's flat and flush and those are fine for semiconductor test is really where we did it the most. We had a 187 mil seven mil thick boards. Six mils drills - don't design that - but it was for semiconductor testing and it had its place in the world. Now, but if you don't know if your via can be filled with the board thickness you have, ask the supplier. They'll ask you the question. How thick is the board? How many layers? What's the via diameter I will be drilling with, and then they'll say, yeah, I could fill that or, no I can't fill that. Instead of having the design and then having it put on hold and then figure out what do we do? Because it may require that you have a bigger land in a bigger drill. And, will it be possible? So, if you have a board that's 125 mils thick, it may be very easy to do via and pad on the land on a one millimeter pitch BGA component, I mean Class 3, but chances are you're not gonna be able to do the same thing on a 0.8mm, because the drill diameter has to be so large.  

J: So is there anything else we need to cover as far as via protection goes? That was really good, thank you. 

G: I would say what's really critical if you're going to do via in pad, where you're going to epoxy and plate over, that you understand the requirements of IPC 6012 for this section. There are particular requirements on the finished board that it needs; the fill, wrap plating and understand wrap plating. If you don't understand wrap plating, I would say contact a board fabricator who you're familiar and comfortable with that does this and have him explain it to you because it's very important to understand what it takes to do wrap plating. What kind of space you can do it in, for example, you’re adding two-tenths of extra cover, so instead of using a half-ounce to start which is point seven mills, go to three-eights its 0.5 - so the extra you add, you can reduce the starting copper but you'll get it back by the wrap plating, so there are certain things that you can do to reduce the risk or the complexity by adding it - but just know that there are process steps that are involved and it's easy to process and be out of the allowance and then you scrap the panels and build more but we understand the risk. Usually, there's more overage when there's epoxy filled, and then multiple epoxy filled processes.

J: Yup, well thank you so much this has been really rich, and will you share with us? I know you have to buy standards, so maybe we can link out to those standards? So well, go to your board manufacturer. I think my mantra and I think in concluding here, is you know my mantra for many years as being a person that sold bare boards was, “talk to your board fabricator.”

G: There was one more subject.

J: Oh, okay.

G: And that was, encroached solder mask clearances, which is a great topic.

J: Okay! So when the solder mask is coming onto the pad?

G: Right, but not over the hole.

J: Yes of course.

G: This is an excellent option. Typically, you have a land, a via and then drill it and the solder mask is two or three mils away from the land - standard. But sometimes that's very close to a BGA component. So, to gain more solder mask distance or more web, you can encroach the solder mask on top of the land, but not in the hole. And so what you want to do is if you’ve called out a drill diameter for the via and the land - ten - is to put an encroachment solder mask clearance of sixteen. So this is smaller than the land itself but bigger than the drill, and any solder that gets in there will wick away from the hole to the land that you don't want to short. You can't trap moisture, you can't trap any debris in there. Because it's not on both sides and it's an excellent solution, a lot of smart designers use this strategy.

J: Okay, that is a good point. And I do see that more and more, it seems like, which is sort of newish to me since I've been out of that for a while. So well, thank you again, Gerry, this has been great. We really appreciate it. And Jesus and all of you listening out there, we hope that that's been helpful. And again, always be certain to talk to your board partner or manufacturer we’ll be sure to share all kinds of links and goodies with you in the show notes. So thanks again for tuning in today to the OnTrack Podcast. Be sure to, like, subscribe, comment and like Jesus, today, when you comment, we're happy to address your questions directly. So thanks again for joining we'll see you next time. Until then, remember to always stay on track!

About Author

About Author

Judy Warner has held a unique variety of roles in the electronics industry for over 25 years. She has a background in PCB Manufacturing, RF and Microwave PCBs and Contract Manufacturing, focusing on Mil/Aero applications. 

She has also been a writer, blogger, and journalist for several industry publications such as Microwave Journal, PCB007 Magazine, PCB Design007, PCD&F, and IEEE Microwave Magazine, and an active board member for PCEA (Printed Circuit Engineering Association). In 2017, Warner joined Altium as the Director of Community Engagement. In addition to hosting the OnTrack Podcast and creating the OnTrack Newsletter, she launched Altium's annual user conference, AltiumLive. Warner's passion is to provide resources, support, and advocate for PCB Design Engineers worldwide.

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