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    Back Drilling in Altium Designer: One of the Easiest Ways to Improve Signal Integrity

    October 22, 2020

    Download the PDF to keep learning offline

    Over the last 20 years, electronic devices have become increasingly sophisticated. Less than two decades ago, just having a mobile phone to make calls was rare; today, our phones power our lives. To meet the growing demand for smartphone technology, technology has become faster, more functional, and intuitive. Improvements to the component base have streamlined processes while reducing manufacturing costs.

    Smartphones use higher-frequency signals, resulting in an increase in processing speed and a decrease in signal edges. Engineers have had to adapt to new challenges caused by a reliance on higher-frequency spectrums.

    PCB designers creating the boards for these devices are facing new challenges as technology advances. They’ve had to move beyond simply connecting component outputs on PCBs according to schematics to ensure that signal propagation paths preserve integrity and that signal losses are minimized. To accommodate these needs, designers must carefully select materials to create boards as well as calculate, and verify impedance.

    If the data transmission rate reaches several gigabit per second (Gb/s), the designer must completely exclude or minimize the heterogeneity that may occur in the signal path. Any heterogeneity may significantly change the wave shape, the integrity of the signal and affect the device functionality. This is particularly true for signals that pass through vias, especially when part of the via remains untapped. This part is heterogeneous and has a negative effect on the signal as shown below (Fig.1).



    Fig. 1. The signal passes through the via. A portion of the via between the 4th and 6th layers is not used and creates a stub.

    Some studies [1] have illustrated the strong influence of the unused part of the via on the quality of the high-speed signal (Fig. 2).



    Fig. 2. The effect of the via stub on the quality of the high-speed signal. The longer stub on the left illustrates substantial distortion that compromises signal integrity. Photo courtesy [1].
     

    Multiple reflections from heterogeneity distort shapes, so designers have to match the impedance of the transmission lines. In some cases, this may be performed in the form of modifications after the PCB has been manufactured. There are different ways of matching the impedance, such as serial termination with a single input resistor, parallel matching by output resistor, matching by voltage divider and many other methods.

    Termination methods require the use of additional components, which is sometimes difficult to implement, especially in dense printed circuit boards. To reduce the number of vias, the designers are trying to provide high-speed signals in one layer. But with the increased density of PCB assembly and the intention of designers to reduce the dimensions of the devices, this approach can be challenging.

    Altium Designer can help the engineer to improve the quality of high-speed signals in a rather simple way; one such method is called back drilling technology. The unused part of the metallization hole is drilled at a larger diameter to a certain depth. In the example below, the designer has to exclude the unused part from 6 to 4 layers (Fig.3).

    Fig. 3. Copper is drilled out from 6 to 4 layers.

    Back drilling can be done from both sides and to a different depth (Fig. 4).


    Fig. 4. Different back-drilling methods.

    When using back drilling, the designer should remember that the distance from the back drill to the components and topology elements recommended by the PCB manufacturer must be maintained. It’s usually a little bigger than a standard via.

    Designers may be unsure as to how to implement back drilling in computer-assisted design systems and what data should be transferred to the PCB manufacturer. Configuring back drills in Altium Designer is very simple.

    The first step is to run the Layer Stack Manager (LSM) and select Back Drills in the upper right corner of the Features section (Fig. 5). With this simple sequence, the designer activates the functionality to use these types of holes.

    Fig. 5. Back Drills in the LSM

    Any quantity of back-drilling holes can be created in the Layer Stack Manager (Fig. 6).


    Fig. 6. Holes with back drilling in the LSM.

    Drilling setting is adjusted using the back drill properties panel in the LSM (Fig. 7).


    Fig. 7. Back Drill properties panel.

    The designer specifies First layer (the beginning of drilling) and Last layer (the layer on which the drilling ends). If the checkbox is enabled for Mirror, the drilling will be symmetrical, e.g., on both sides (Fig. 8).

    Fig. 8. Drilling on both sides.

    Designers must also define which nets are to be back drilled. This process is implemented using Design Rules. In the High Speed section, select Max Via Stub Length (back drills) and create a new rule (Fig. 9).
     

    Fig. 9. The rule for back drills.

    The designer defines conditions of back-drilling operation, assigns how much larger the drilling diameter should be relative to the main hole, the maximum allowed length of the remaining via stub and the object to which this rule will be applied. The object may contain nets, net classes, and xSignals. When the condition specified in the rules is activated, the back drilling is automatically added.

    Back drills in 2D mode on the printed circuit board will be indicated as follows (Fig. 10):


    Fig. 10. Back drill displayed in 2D mode.

    The back drills are double-colored. One color is the color of the layer where drilling starts; the other is the color of the layer where drilling ends. This indication ensures the designer can easily navigate to the back drill location.

    Back drilling is also displayed in 3D mode (Fig. 11):


    Fig. 11. Back drills displayed in 3D mode.

    Information about back drilling is needed for the PCB manufacturer. This information is displayed in the Drill Table in both the PCB file and Draftsman Document, as well as in the output Gerber files and NC Drill files (a separate file is generated for back drills). A fragment of the table obtained in the PCB Editor is presented as an example (Fig. 12).


    Fig. 12. Table fragment including back drill.

    The above example contains the hole diameter, symbol, first, and last layers and other relevant information. The designer can also adjust the display of sections, as in a more typical drill table.

    The list of documents and files required for back drilling includes specific items:

    1. NC Drill file for back drilling
    2. PCB drawing with back drilling holes
    3. Back drilling placement in the PCB structure (first layer and last layer)

    In Altium Designer, back drilling is easy to configure. The designer can use it quickly with the help of simple settings, effectively improving the quality of a high-speed signal.

    REFERENCES

    1. https://blog.lamsimenterprises.com/2017/03/08/via-stubs-demystified/
    2. https://www.signalintegrityjournal.com/articles/1731-signal-integrity-characterization-of-via-stubs-on-high-speed-ddr4-channels
    3. https://www.multi-circuit-boards.eu/en/pcb-design-aid/mechanics/backdrill.html
    4. https://www.keysight.com/upload/cmc_upload/All/2_Demystifying_Vias_in_High-Speed_PCB_Designs.pdf
    5. http://agata.pd.infn.it/LLP_Carrier/New_ATCA_Carrier_web/Assemby_Docs/Backdrilling.pdf
    6. https://www.altium.com/documentation/altium-designer/pcb-dlg-maxviastublengthrule-framemax-via-stub-length-back-drilling-ad

     

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