How to Avoid the Most Common Errors in Your Schematic Design Process

A Decade of Differences

Schematic designs review processes were a lot simpler 10 years ago, and the schematic review process to check for errors didn’t seem to require such a huge dedication of man-hours. Over 10 years later, our designs have become more complex than ever. And when it comes to designing complicated circuits, with multiple high-pin count devices and large on and off-board connectors, there comes a considerable risk for errors to escape into the manufacturing process.

And we all know what that leads to, respins.

I recently sat down with Altium Designer to talk about the new technology we are working on at Valydate for Schematic Integrity Analysis checks. In the past few years, we’ve found ourselves profiting greatly from all the errors engineers make in the schematic design process. It’s great for us, and great for designers as well, as we’ve finally received some clarity on just how many potential errors there are in the schematic design process, and how few of them are actually being identified in manual, human-based reviews.

Starting Small

Valydate has an interesting history. We began with the intention to release an EDA tool for Schematic Integrity Analysis but just weren’t big enough at the time to make that kind of investment. The solution? Start with a smaller investment, develop our technology through a service-based offering and show off our technology through the evaluation of real client projects.

Did it work? Yep. Big time. Report after report came back from our client projects on similar errors that designers kept making in their schematic review process, some of which you might find that you are making yourself.

Finding Ground in Design Flaws

Valydate spent two years, from 2011 to 2012 running schematic verification reports for hundreds of schematics. We split up our findings into two categories:

• Critical errors. These included errors in a schematic that, if left uncorrected, will most likely cripple a design.
• Defects. While not as severe as critical errors, defects left uncorrected still had the chance to cause loss of functionality in a device.

Critical Design Errors

We were surprised about the kind of critical, design-breaking errors we were finding in our schematic review checks. A whopping 21% of total critical design errors were related to a missing power source, with 18% of errors related to having multiple outputs on a net. Have you ever made these mistakes in your design process?

Defect Errors

Defects also provided some interesting insights, with the range of potential defects being far greater than critical errors. The most of them all? Driver voh being lower than receiver vih at 22%. Do any of these look familiar to you?

The Link

What I found most fascinating as we neared the completion of our 2-year study is the commonality between the design errors. It’s not like design team is making one-off mistakes here and there. There were hundreds of different schematics in this study, and all of them had the same design-breaking flaws.

I don't necessarily think it’s the designer’s fault. There’s just too much ground to cover in today’s schematic design reviews. When it comes to meeting a release window, errors are going to slip through the cracks. Overall, there’s just way too many human-based variables to consider in the schematic review process. How do you ever know what caused a design flaw to slip through to manufacturing?

Practical Solutions for Designers

After concluding our 2-year long study, we noticed a trend with the most frequent design errors - they all involved power nets, programmable devices, and improper pullup/down resistors. Schematic analysis tools aside, we’ve compiled 8 practical tips for designers to keep in mind the next time they are designing a schematic to hopefully avoid some or all of these design-breaking errors.

Power Net Solutions

• When designing your schematic, make sure that each required printed circuit board voltage has a defined power source with a consistent net name, otherwise you might risk the chance of misconnects if names aren’t exactly the same.
• Be sure to inspect the power pins on each device to confirm they are connected to a power source with a correct minimum and maximum voltage.
• Always take an inventory of all the grounds in your schematic, and confirm that each ground net has a specific ground source.
• Make it a habit to check that your device’s schematic symbols include tabs on the schematic that will be reviewed by a human, and always use the same pin reference that appears on your datasheet.

Programmable Devices and Missing Resistor Solutions

• If you are utilizing a programmable device in your design, confirm that your circuit board netlist is calling for a connection with the device with a correctly defined pin.
• Verify that your programmable pin definition does not conflict with the definition required by your PCB layout. Mixing up pin configurations can lead to errors when a pin for an FPGA is defined as an output, but you set it as an input.
• Establish a communication channel with your FPGA desi teams as early as possible in the design process to communicate the pin-by-pin expectations of pin names, direction, technology, pullup/down presence, and power bank voltages.
• Take the time to verify that all open-drain nets in a design are covered at the very least with a provision for pullups/downs.

A Matter of Time

At the end of the day, I think it really comes down to how much time you are willing to invest in your schematic review process. While the human-review process worked great a decade ago, we are now at a place where schematics are just too complicated to reliably verify by hand.

What we really need to see is a Schematic Integrity Analysis tool that can run all of these checks for you, and free up your time for more pressing matters. Valydate is doing just that, and in the weeks ahead we are excited to share a new extension for Altium Designer^® that will automate the schematic review process for you. Stay tuned, Altium Designer users, there are good things ahead.

Michael is an accomplished business leader with a track record of increasing revenues, profits and market share while driving high levels of customer and employee loyalty. He is equally capable of directing cross-functional global R&D teams.

Prior to Valydate, Michael held a variety of management positions in Business Development, Sales, Operations, and Engineering within Nortel Networks, CoreSim and most recently Fidus Systems where he led the company’s expansion into Silicon Valley. He is currently the CEO of Valydate, a company he co-founded in 2010.

Michael received a Bachelors of Computer Systems Engineering (High Distinction, Senate Metal) from Carleton University and an Executive Masters in Business Administration from the University of Ottawa. He is the recipient of many honors and awards including the OBJ 2009 Forty under Forty Award.