The “Mini Monkey” Board – Using the LPC55S69 in the VFBGA98 Package

For as long as I can remember, I have been a microcontroller addict. In 2020 there is no shortage of component selection. We are also at an interesting period where MCUs can tackle complicated tasks that we may have chosen a high-end applications processor for. Quite a bit of my career has been focused on doing really awesome things in the MCU space as you get a great balance of cost, design control, and simplicity. I am always on the lookout for the next “thing,” and the NXP LPC55 family caught my attention. One particular variant is the LPC55S69, which packs multiple CPU cores, a dedicated DSP engine, and a general-purpose encryption engine into a single, small package. I wrote a series of articles on some of the neat features.

Many new projects start with development boards (such as the LPC55S69-EVK) to evaluate a platform and take the 1st cut at some software development work. Getting to a form-factor compliant state quickly can be just as crucial as the firmware efforts. Getting a design into a manufacturable form is a very important step in the development process. I like to address all of my “known unknowns” early in the process with new hardware, so I almost always make my test PCBs right away. The LPC5500 series devices are offered in some easy to use QFP100 and QFP64 packages. Designers also have the option of a small VFBGA98 package option. Many engineers flinch when you mention BGA, let alone a “fine pitch” BGA. I hope to show you that it is not bad as you may think, and one can even route this chip on 2 layers and use a low-cost assembly service to build the prototype.

The LPC55S69 is offered at an attractive price but packs a ton of functionality and processing power into a tiny form-factor that uses little energy in both the active and sleep cases. Having all of this processing horsepower in a small form-factor can open new opportunities. Let's roll up our sleeves and see what we can get done with this new MCU.

I want to step through a design with the LPC55S69 in the VFBGA and actually build something in this series of articles. This design's scope will be limited to some basic design elements of bringing up an LPC55S69 while offering some impressive IO for visualizing signal processing with the PowerQuad hardware. Several years ago, I posted some projects on the CircuitMaker community using the Kinetis FRDM platform. One of the projects showcased some simple DSP processing on an incoming audio signal.

The “Monkey Listen” project used an NXP K20D50 FRDM board with a custom “shield” that included a microphone and a simple OLED display. For this effort, I wanted to do something similar except using the LPC55S69 in the VFBGA98 package with some beefed-up visualization capabilities. There is so much more horsepower in the LPC55S69, and we now have the potential to create neat applications like real-time feature detection in an audio signal. Given the copious amounts of RAM in the LPC55S69, I wanted to step up the game a bit in the display. The small VFPGA98 package presents with an opportunity to package quite a bit in a small space. 

I recently found some absolutely gorgeous IPS displays with a 240x240 pixel resolution from buydisplay.com. They are only a few dollars and have a simple SPI interface. I wired a display to the LPC55S69-EVK for a quick demonstration:

It was difficult for me to capture how beautiful this little 1.54” display is with my camera. You must see it to believe it! Given the price, I figured I would get a boxful to experiment with!

The overarching design concept with the “Mini Monkey” project is to fit a circuit under the 1.54” display that uses LPC55S69 with some impressive IO:

• USB interface with access to the bootloader
• LIPO Battery and charger circuitry
• Digital MEMs microphone
• SWD debugging
• Buttons
• Access to the on-chip ADC

I want to pack some neat features beneath the screen that can do everything the “Monkey Listen” project can, just better. With access to the PowerQuad, the sky is the limit on what kinds of audio processing that can be implemented. The plan is to see how much we can fill up underneath the display to make an interesting development platform. I started a project in Altium Designer and put together a concept view of the new “Mini Monkey” board to communicate some of the design intent:

I like starting with “concept” boards as I can flush out ideas quickly. Using Altium makes quick work of the process and allows be to hash out some of the details before I commit.

Combining MCUXpresso and Altium for Quick Part Creation

Combining some features in MCUxpresso with my PCB tool of choice, Altium Designer, I can significantly reduce the time in the component creation process. The first step in designing a PCB with a new MCU is to add the part to your component libraries. Component library management can ignite passionate disagreements between design engineers. My view on library management is rooted in many years of making mistakes! With a strong desire to “save time,” these simple mistakes ultimately caused delays and made projects more complicated than needed. Given my experience, there are a few overarching principles I adhere to.

1. The individual creating the component should also have to stay the weekend and cut traces if a mistake is corrected. The concept conflicts with the “librarian/drafter” model, but I have seen projects where the librarian made a mistake on a 1000+ pin FPGA that cost over $5,000. This model was put in a library and marked as “verified.” In this case, the drafting teams claimed they had a process that included a double check, but no one in that process knew the context on how the part was going to be used. This was an extreme case, but I like everyone to have responsibility for the outcome.
     
2. Pulling models from the internet or external libraries is okay as a starting point, but it is just that: a starting point. You must treat every pin as if it is wrong and verify. Since many organizations have specific rules on how a part should look, you will need to massage the model anyway to meet your own needs. Software engineers shake their heads at this rule. “Why not build on somebody else’s libraries? It is what we do!”. Well, a mistake in a hardware library can take weeks, if not months, to solve. The cost, time, and frustration impact can be huge. We hardware engineers can’t merely “re-compile.” I don’t trust any footprint or symbol unless I know it has been used in a successful design.
    
3. I believe the design reused is best done at a schematic snippet level, not an individual part. After all, once I get this Mini Monkey board complete, I will never again start with just the LPC55S69. I want all the “stuff” surrounding the chip that makes it work! For complicated parts such as a high-end FPGA, there is quite a bit of engineering in the part’s powering and bootstrapping. That data is just as useful to capture as the pinout and footprint.
    
4. To the casual observer, these principles seem onerous and time-consuming, but I have found that they save me time over the project’s course. Making your own parts may seem time-consuming, but it does not have to be. Some tools can make your life simpler, and the task less arduous. Also making your own CAD part is useful for a few other reasons:
    
   1. You have to go through a mental exercise when looking at each of the pins. It forces you brain to think about functionality in a slightly different way than just looking at the user manual. When starting with a new part/family, repeated exposure is a very good way to learn.
       
   2. Looking at the footprint early on gets your brain in a planning mode when you get started with the routing.

One could argue that this is “lost” time compared to getting someone else to execute the library management, but I feel strongly that it saves time in the long run. I have witnessed too many projects sink time into unnecessary debugging due to the lousy CAD part creation. I feel the architect of the design needs to be intimately involved.

The LPC55S69 in the VFBGA is only 98 pins. Without automation or tools, it would not take all that long to build a part right from the datasheet. However, it is on the edge of a time-consuming endeavor. When I build schematic symbols, I tend to label the pins with all possible IO capabilities allowed by the MCU pin mux. This can make the part quite large, but it also helps see what also is available on a pin if you are in a debug pinch. Creating pins with all this detail can be quite time-consuming. I use Altium Designer for all of my PCB designs as it has some useful automation to make parts more quickly. NXP’s MCUXpresso tool also has a unique feature that can really help board designers get work done quickly.

Built into MCUXpresso is a “pins” tool that helps set up the pin mux and do some advanced planning. While it is primarily a tool for bootstrapping pin setup for the firmware, It is also useful to drive the CAD part creation process. Simply create a new project and start the pins tool:

The pins tool shows you both a tabular and a physical view of pin assignments. This is useful when planning your PCB routing. We will use the export feature to get a list of all the pins, numbers, and labels.

The pins tool generates a CSV file that you can bring into your favorite editor:

Not only do I get the pin/ball numbers, I get all of the IO options available via the MCU pin mux... With just a few modifications, I can get the spreadsheet into a format useful for the Altium Smart Grid Paste Tool.

Altium requires a few extra columns of meta-data to import the data into a grouping of pins in the schematic library editor. At this point, you could group the pins to your personal preference. I like to see all the schematic’s pin functions, but it does create rather large symbols. The good news here is that by using MCUXpresso and Altium you can make this a 10 minute job, not a 3 hour one. Imagine going through the reference manual line by line!

Viola! A complete symbol. It just took a few minutes of massaging to get what I wanted. Like I stated previously, a 98-pin package is not that bad to do manually, but you can imagine a 200 or 300 pin part (such as the i.MX RT)!

The VFBGA package is 7mmx7mm with a 0.5mm pitch. There are balls removed from the grid for easier routes escaping when using this part with lower-cost fabrication processes.

Once again, with a quick look at the NXP documentation and using the Altium IPC footprint generator, we can make quick work of getting an accurate footprint.

The IPC footprint generator steps you through the entire process. All you need is the reference drawing.

A quick note about the IPC footprint tool in this use case: the NXP VFBGA has quite a few balls removed to allow easier escaping. The IPC footprint generator can automatically remove certain regions. I found that this particular arrangement needed a few minutes of handwork to delete the unneeded pads given the unique pattern.

Using Altium and NXP’s MCUXpresso tool together, I was able to get my library work done very quickly. And because I spent some time with the design tools, I became more familiar with the IO’s and physical package. This helps get the brain primed for the design work.

At this point, I have a head start on the schematic entry and PCB layout. Next time we will dive in a bit to see what connections we need to bootstrap the LPC55S69 to get it up and running. We will look at some of the core components to get the MCU to boot and some peripheral functions that will help the Mini Monkey come alive!

Rev A Build and Moving onto Rev B

I often say it was a great time to be an engineer! Why? Because it has never been easier to get your hardware built at a low cost. I like to iterate quickly on new concepts, and there are plenty of services to help. For Rev A of the Mini Monkey, I chose Macrofab. One of the stated objectives in this project was demonstrating the use of the VFBGA98 package in a low-cost process. The Mini Monkey spec’s fit within the lowest cost tier, so I figured that I would give them a try. The Mini Monkey board will also be used to show off some of the PowerQuad DSP engine's neat capabilities in future design blogs. Here is what we ended with for the first version:

Highlights

• Lithium-Polymer battery power with micro-USB Charging
• High-speed USB 2.0 Interface
• SWD debug via standard ARM .050” and tag-connect interface
• Digital MEMs microphone with I2S Interface
• 240x240 1.54” IPS Display with HS-SPI interface
• Op-amp buffer for one of the 1MSPS ADC channels
• 3 push buttons.  One can be used to start the USB ROM bootloader
• External Power Input
• 16MHz Crystal
• 11 dedicated IO pins connected to the LPC55S69.   Functions available:
• GPIO
  • Dedicated Frequency Measurement Block
  • I2C
  • UART
  • State Configurable Timers (Both input and output)
  • Additional ADC Channels
  • CTIMERs
• The HS-SPI used for the IPS display is also brought to IO pins

I am a firm believer in not trying to get anything perfect on the 1st try. It is incredibly inexpensive to prototype ideas quickly, so I decided to try to get 90% of what I wanted in the first version. Without too much trouble, I could get everything I wanted on 2 signal layers with filling in a power reference on the top and bottom sides. If this were a production design, I would probably elect to spend a bit more to get two inner reference planes using a 4-layer design. Once a design hits QTY 100 or more, the cost can be negligible, and it makes the design much easier to execute and compliant with EMI, RFI specs. For most of my “industrial” designs, I always start at 4-layer unless it is a simple connector board.    

For this 1st run, I wasn’t trying to push the envelope with how much I could get done with low-cost design rules and a 2-layer design. The VFBGA leaves quite a bit of space for fanning out IO. Quite a bit can be done on the top layer. I had a few IO that ended up in more challenging locations, but this was a quick route on the first try.

As you can see, I did not make use of all the IO. If I had used a 4-layer board, I would be able to get quite a bit more of the IO fanned out. Moving to smaller vias, traces, and a 4-layer stack-up would probably allow one to connect all IO’s. For this design, I was trying to move quickly and use the standard “prototype” class specs from Macrofab. This means 5-mil traces, 10-mil drills with a 4-mil annular ring. If you can push to 3.5mil trace/space, NXP AN12581 has some suggestions.

I did want to take a minute to talk about Macrofab. I normally employ a local contract manufacturer’s services, but this time I elected to this online service a try. After going through the order process, I must say I was thoroughly impressed! The online web application made ordering a breeze. 

The 1st step is to upload your PCB design files. I use Altium Designer PCB package, and Macrofab recommends uploading in OBD++ format. Since this format has quite a bit more meta-data baked in than standard Gerbers, the online software can infer quite a bit about your design.

The Macrofab software gives you a cool preview of your PCB with a paste mask out of the gate. Note that this design uses a red solder mask, as that is what is included in the prototype class service. Once you have all the PCB imported, you can now upload a Bill of Materials (BOM).

Macrofab provides clear guidance on how to get your BOM formatted for maximum success. Once the BOM is uploaded, the online tool searches distributors, and you can select what parts you want to use (or leave items as Do No Place). I was impressed that it found almost everything I wanted out of the box. Pricing and lead time are transparent.

Next up is part placement:

Using the ODB++ data, the Macrofab software was able to figure out my placements. I was thoroughly impressed with this step, as it was completely automatic. The tool allows you to nudge components if needed. Once placements are approved, the tool will give you a snapshot of the costs.

What I liked here was how transparent the process was. Using the prototype class service, a single board was $152. This is an absolute steal when you consider that parts and PCBs are baked in all of the setup costs. If you believe in the value of your time, this is an absolute no brainer. I also like that it gives you a cost curve for low volume production. In the future, I am going to have a hard time using another service that can’t give me much data with so little work. I ended up ordering three prototype units. Total cost plus 2-day UPS shipping was $465.67. Note: I did end up leaving one part off the board for now: the 1.54” IPS display. This part requires some extra “monkeying” around as it is hot bar soldered and needs some 2-sided tape. I decided to solder the first three prototypes on my bench to get a better feel for the process of using this display. However, I am more than happy to push the BGA and SMT assembly off to someone else.

Rev A Results:

I did post a video here showing the results located here.

Like all first versions, there are things I needed to fix! It is common for engineers to have a bit of “imposter syndrome” and beat themselves up for not getting everything right on the first try. I certainly do my best to achieve stated specifications, but always keep in mind that it generally takes three iterations to get a final product. When using a new part, especially ones with reference manuals with thousands of pages, it is easy to miss details, even with a team working on a project. Quick iteration will allow you to discover your “known unknowns” quickly. 

Moving on to Rev B

Board bring-up is on the first revision of any design, especially when using a new microprocessor. I always start with board-level power and then move on to my MCU debug interfaces. Rev A of the Mini Monkey had a pretty simple power supply. It was comprised of a Li-Po Battery with a charger and an LDO. In this case, I elected to use the LDO as my voltage drop would be less than 1v in most cases, and the actual current consumption would be small. The LPC55S69 is built on 40nM technology and consume a small amount current. I measured @5mA running at 150MHz with the PowerQuad FFT engine continuously running! Also, this particular circuit configuration was pulled from another known working design:

Everything came up without issue. The charger circuit worked as expected, and I had a clean +3.3v rail. Once I saw the power supply was running, I checked that the core supply for the LPC55S69 was correct. The LPC55S69 has a mini DC-DC converter to generate the core voltage (@1.2v).  

Once I verified the power supplies’ correct operation was verified, it was time for the real moment of truth. Can I program via a SWD connection?

This was where I found my only real “bug” in Rev A.

I was having trouble connecting via SWD over my Segger J-Link. Turned out to be a pretty simple issue in that I forget to connect my “RST” netlabel to the proper net on the LPC55S69. I like to place large warning graphics on my schematics. It is a simple visual warning on the schematic to remind me to fix the next reversion issue. Lucky for me, patching the reset line was quite easy, and I was up and running. I have executed many MCU designs with lots of different types of programming interfaces. We all still make mistakes, just make them early! 

The other significant change for Rev B was with the USB interface. The LPC55S69 has 2 USB interfaces. Both of which can be used with the ROM bootloader. I wanted to enable programming via the USB interface, so I made sure to wire it up. I chose USB0 as the pads were in a very convenient section of the chip. The distance to the USB connect was approximately 250mils from the USB0 balls on the LPC55S69.

My USB circuit did work okay, but unfortunately, there was no clear documentation in the manual that USB0 required an extra step to use with the ROM bootloader at the time of the schematic entry. By default, it was disabled, and the customer must program a special region of flash. The particular flash location is sensitive as other bits in the register could potentially disable all access to the chip (security!). I wanted a good out of the box experience, so I elected to move to USB1 for future revisions. This is an excellent example of reading the entire reference manual and not knowing where all your issues will be. At the time, it was not documented clearly, and you had to contact NXP support. While there was a workaround, testing was what revealed the issue. For Rev B, I will use the USB1 interface, but the connections are not as convenient with way parts are currently placed.

A quick note on the USB routing is the best practice to control the differential impedance on the D+/D- lines to 90 Ohms. This best done with a 4-layer PCB where your reference layer is on layer 2 or layer 3. Layer two in a 4-layer stackup is usually only one pre-preg distance (5 to 10mils depending on the process) away from your transmission lines on the top layer. The required trace widths and spacing are reasonable. I was trying only to use a 2-layers in this first effort. Since my connection was so short, controlling impedance was not as important as we were quite a bit below the stub length. Eric Bogatin has some good rules in his article How Long a Stub is too Long?: Rule of Thumb #18.

The effects of other obstacles on the top layer along the 250mil length would render most of your computations useless without employing a field solver. If I had to route the differential pair on the order of inches, I would be more concerned. Since I am using the USB in full speed mode (12MB) so I wasn’t quite as concerned for this initial revision.

So, moving forward with Rev “B”. I want to fix up a few minor issues to make some user experience more convenient as well as fix the reset bug. For this run, I am going to try a different service: PCB:NG.

They have a similar web interface for uploading and checking your design. PCB:NG pricing is quite attractive, and the specifications for this board appear to fall within there “standard” build flow. Below is an unboxing to show the quality and functionality of the product that arrived!

Would you like to find out more about how Altium can help you with your next PCB design? Speak to an expert at Altium.