Customizing Performance-Based Electrical Design Rules in Altium Designer
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Determining the correct electrical design rules in your ECAD software is essential for effective electronics design. Correctly determined PCB design rules ensure a design can be manufactured with high yield and components can be assembled. Many electrical design rules come from PCB manufacturers and IPC standards, but electrical design rules go beyond manufacturing and assembly. PCBs also require electrical design that account for signals’ electrical behavior. Critical traces might require several custom electrical design rules to ensure signal and power integrity, as well as manufacturability.
For example, a PCB might have an electrical design rule where most of the routing has a common clearance requirement based on calculated allowable crosstalk. This may also contain a group of other traces that are extremely sensitive to all noise and thus require special attention regarding crosstalk and noise coupling. For these noise-sensitive traces, we need wider clearance—a different design rule—rather than the common clearance design rule. To ensure the design rule check (DRC) accurately analyzes this critical area of the PCB, we need to have unique performance-based electrical design rules for these sensitive traces.
Altium Designer® has options to define custom design rules for specific traces. In this article, I describe one of my methods for defining design rules which are based on the Altium Designer Class function. I go through a step-by-step workflow for assigning traces in a class and how to set design rules for the created class.
Electrical design rules are best defined when designing schematics. From the schematic, you can identify which nets carry important signals and require specific electrical design rules. These can be high-speed signals, signals requiring controlled impedance, signals requiring special clearance to other nets, or even components requiring certain clearances. In many of my capacitive sensor designs, I need two different clearance rules for sensor signals: one for the sensor electrode, and another for traces being routed to the sensor.
Regardless of the signal type and electrical design rule it requires, design rules are most easily organized by creating an individual class for signals requiring the same design rules. If you have several groups of signals, each requires its own class. Net Classes can be created in Altium Designer by selecting the Place Directives Parameters Set. Now you could place this directive for signals, but before placing it anywhere, press the tab key, which opens the Properties window. In that window, you can define a label for this particular class, which you will only see in the schematic. To create the class, select from the bottom part of the Properties window, click Add, and from there click Net Class as shown in the image below.
Next, in the Parameters window, enter a unique name for this new class that provides a good description. This same name will be seen later on when creating the electrical design rule involving this class, so it is worth using a name which helps you to identify it.
Now you can place this determined directive for all signals that require specific design rules. Signals classified are marked by a red circle with the label you determined earlier.
After updating the schematic into the layout, the nets in the layout have the same classification as made in the schematic. All physical and electrical design rules are defined in the PCB Rules and Constraints Editor dialog. Here we select the rule we want to define, and as an example, we select the Electrical clearance rule. We create the new rule and give it an appropriate name. In the where the object matches the field, we select Net Class, and we select from the list of the classes, the one we defined in the schematic.
The above window shows that, for this particular class, there is a clearance rule that only applies to the selected class, and now we can set the clearance rule between nets in this class and all other design rules. In this case, we set a 1 mm clearance to other traces, and we select "All" in the "Where the Second Object Matches" field. This determines clearance from traces of the Sensitive signal class must be at least 1 mm from all other features in this layout.
The reasoning for this particular design rule might account for manufacturability, or it might account for electrical behavior. Design rules should try to balance both. Modern PCB manufacturers can fabricate feature sizes much smaller than 1 mm as a standard capability, so the electrical design rule in this case is purely to ensure that the signals on these nets receive as little noise as possible via crosstalk.
Next, I determine a second clearance rule for the same Sensitive signals, meaning the minimum allowed clearance between signals belonging to this particular net class. I create a second design rule and give it a different name, Sensitive signals int. I determine the "Where the First Object Matches" in the same way as with the first rule, then I select "Net Class" but in the "Where the Second Object Matches" field, and from the list I select the "Sensitive signals" class and set the Constraints value to 0.2 mm. This specifies a minimum 0.2 mm clearance for signals belonging to the Sensitive signals class.
Now we have determined two clearance rules for Sensitive signals class that we defined in the schematic side. To get design rules working properly, I need to set priorities for these rules. I need to set priorities such that Altium checks first the clearance between Sensitive signals, then clearance between Sensitive signals and other objects, and finally a general clearance rule for other circuits. Set rule priorities by clicking Priorities in the left and down which opens you a window in which changing priorities of design rules is possible to do.
The image below shows how these clearance rules for my important Sensitive signals class have affected the layout. The five uppermost traces belong to the Sensitive signals class I defined in the schematic. We see clearance between classified signals and ground polygon for the five uppermost traces, which are classified as Sensitive signals, follows the 1 mm clearance rule. Clearance between the polygon and other signals follows the 0.2 mm rule. The 5 traces in the bottom of the window are not part of the Sensitive signals class, so they obey the common clearance rule. When the polygon was poured, Altium's DRC engine automatically checked the polygon pour region and applied all relevant clearance rules to the polygon. Note that this rule was applied even though the polygon was defined throughout the entire window shown below.
Similarly, I can define a width design rule for Sensitive signals. I select the Width rule, create a new rule, and like I did in clearance design rules, I determine this width rule for the Sensitive signals class. Now the width of these traces shall strictly follow the 0.15 mm rule, and this configuration applies that rule only for traces belonging to the Sensitive signal class. All other routing follows the general Width rule.
We see design rule violations after applying this rule, and to clear violations, we must change the width of Sensitive signal traces according to the 0.15mm width rule we just created. Again, the five lower side traces do not belong to classified signals, and the specific width rule is not valid for them.
Now we have determined critical signals in the schematic side, updated this information to the layout side, and defined special clearance and width design rules for our critical signals. This method is easy to implement and efficient for special cases in which design rules differ from the common rules. For polygons, I don’t use any other methods, like adding cutoff areas manually. Also, with this approach, you can determine unique clearances for components connected to traces and unique clearance for the trace itself. I recently participated in Altium’s Length matching in high-speed buses webinar. In this webinar, the same principle was used for matching the length of differential bus signals by defining critical traces in the schematic side using similar classification and then determining layout design rules. I recommend that you watch this webinar to see how to do things in practice and to learn a couple of more tricks not presented in this article, even if you are not designing high-speed buses.
I typically use both manufacturing-based design rules and electrical design rules. PCB manufacturers always have a minimum width and clearance rules for all available copper thicknesses, and these set the extreme minimum limits for the design. Being within the manufacturing window ensures that you get the highest manufacturing yield. However, to get the best performance, you need to follow the physics of electronics and being sure a complex electrical circuit meets the target performance you need to convert physics laws into basic design rules, like clearance, width and length. Following these sounds self-evident, but when the complexity of a PCB increases, following these requirements manually and by visual inspection becomes challenging and soon, the only option is to use DRC features. By determining design rules correctly, you can make sure these rules are followed in all locations of a PCB.
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