Signal Integrity Mastery: Scott McMorrow's PCB Design Revolution

Scott McMorrow, Strategic Technologist for Signal Integrity Products at Samtec Inc. who's well-renowned for his expertise in signal integrity, discusses revolutionary techniques in PCB design on this episode of the Altium OnTrack podcast. 

We delve into Scott's journey in the electronics industry, his approach to overcoming complex PCB layout challenges, and his predictions for the future of signal integrity in PCBs. Learn how Scott's methods are transforming the way designers approach PCB layouts, ensuring optimal performance and reliability. 

Join host Zach Peterson as they explore Scott's influential work at Samtec, his experience in consulting, and the innovative strategies that earned him a nomination for Engineer of the Year at DesignCon. 

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Show Highlights

• Industry Perception Shift: Scott McMorrow highlights the industry's historical oversight of connectors and their crucial role in signal integrity, emphasizing the evolving awareness among designers. 
• Career Trajectory: McMorrow recounts his journey from consultant to his role at Sam Tech, and how he approached signal integrity practices within the company. 
• DesignCon Tutorial: McMorrow previews his upcoming tutorial at DesignCon, focusing on advanced PCB connector and package launch design processes, dispelling myths and providing practical insights. 
• Problem Solving: McMorrow introduces a systematic approach to address complex design challenges, transforming unpredictable "whack-a-mole" issues into manageable and controllable design elements. 
• Expert-Guided Design Masterclass: McMorrow outlines a comprehensive and innovative workflow for optimizing via designs, incorporating expert guidance and simulation tools to streamline the design process and ensure manufacturability. 

Links and Resources

• Follow Scott on LinkedIn
• Watch more informative videos about signal integrity on Altium Academy
• Read this article, Crosstalk Basics in PCB Design

Transcript

Zach Peterson:
The way I use the kind of simulation for these types of transitions is on the front end, you prepare what you envision the transition to look like for your stackup and give that to the layout person. They're going to implement that where it needs to be implemented and then they work around that. So you really use it as a constraint. Is that your thinking here as well?

Scott McMorrow:
It is, but I'm modifying that constraint a bit. So the first off is constraint. Number one is what's the connector that you're using? And so basically we basically prepackaged that so that you basically load in the connector type you want and a functional breakout is actually generated.

Zach Peterson:
Hello everyone. Welcome to the Altium OnTrack podcast. I'm your host, Zach Peterson. Today we'll be talking with Scott McMorrow, strategic technologist for signal integrity products at Sam Tech. Scott is up for engineer of the year award at DesignCon, and we're going to talk to him about his journey through the electronics industry and what he'll be doing at DesignCon this year. Scott, thanks so much for joining us.

Scott McMorrow:
Oh, thank you for having me, Zach.

Zach Peterson:
Absolutely. I feel like you and I have probably conversed over SI lists at some point, and I see you post there. I'm sure you probably have seen me post there a time or two, so it's good to actually see each other face-to-face, even if it's mediated by a camera.

Scott McMorrow:
It is, it is.

Zach Peterson:
So just to get started, I always like to learn a little bit about people's journey into electronics. So maybe if you could just briefly tell us about your background and then how you got started in electronics.

Scott McMorrow:
Sure. Well, as a kid, my father was an electronic technician and electronics engineer for the Federal Aviation Agency and designed some pretty cool things including instrument landing systems back in the sixties. And that got me interested in engineering and electronics. So I went to Virginia Tech, my local Virginia school and got a degree in electrical engineering in the, well. I actually finally graduated in 1980. I took a few years off and went and repaired stereos for a couple of years, decided that repairing stereos is a good career choice and that I really did want to be an engineer. So I went back, created my own curriculum with electives, which was in the late seventies. That was one of the first computer engineering curriculums. And from there, graduated in 1980 and went on into my engineering career. Started out in aerospace in Denver at Martin Marietta ground support electronics in Littleton, Colorado. And from there jumped from job to job back during the eighties and ended up on the west coast in Oregon at Lattice Semiconductor. And from there I was sort of around the semiconductor industry and found my way into problems that were, we didn't call it signal integrity back then, but they were interconnect problems and started solving them and understanding them. And I've probably been formally a signal integrity engineer since about 1995 or so and have been working in the industry as a signal integrity technologist ever since.

Zach Peterson:
I think that people who are just getting into the industry and who maybe dream of pursuing a career as an electronics engineer, they probably don't really think about connectors or really components in general. I think if they think about components, it's semiconductors. But I've never heard anybody say, I want to go be an SI guy at a connector company. I think the people are very aware of how things like connectors can impact signal integrity, but I think broadly for PCB designers, they're just seen as another mechanical element.

Scott McMorrow:
Yeah, exactly. And in fact, that was the way I looked at it years ago. And I spent most of my career since about 1997 as a consultant. So I worked on platform problems for a variety of hundreds of different customers, different kinds of platforms, digital electronics problems and rf, electronics problems, crosstalk problems, video, pretty much anything that well I could make a buck and get a job at. And in the process, I formed my own company. I worked for a couple of consulting companies and I formed my own around about 2002 and my called Terra Speed Consulting. And my first customer was Sam Tech. And like everybody at the time, Sam Tech is fairly ubiquitous in the industry today, but at that time, if you said Sam Tech, most people said who or Oh yeah, they make those a hundred mils stick pins for headers, for cable headers and things like that.

And I was asked to work with their, they had just started a signal integrity department and I was asked to start working with them on developing what they called final inch, which was they recognized that the connector goes on a board, but it doesn't matter how good the connector is, the final piece of it is that inch in the breakout area of board and that can either give you the best performance or it can limit performance seriously. So we started creating application notes and test boards, and I went on to consult for many, many other companies, but Sam Tech was always a customer year after year after year that was continuous. As I grew my capabilities, their capabilities grew. And then finally 10 years ago, Sam Tech gave me an offer I couldn't refuse and said, we would like you to bring your consulting business into Sam Tech and we'll buy it from you.

So I started out, and at the time I think we maybe had 15 people in the signal integrity department at Sam Tech. We're now over 90 and we've grown exponentially revenue and has gone from a few hundred. When I started working with Sam Tech, there were a 20 million, about $200 million company and years ago, and today we're right around a billion dollars a year in sales. So it's been quite a journey. And what we're now finding is the interconnect doesn't stop at the connector. It is in the board, it's in the vias, it's in the transitions, it's also in the cables. So I had the good fortune of working with our cable plant in Wilsonville in designing the high performance IPE twin X that we use, that's our next generation I speeded Air is going to be running 224 gigabits per second in applications, in systems. So we kind of look at all of those things and have encompassed that in what we do at Sam Tech.

Zach Peterson:
Yeah, Wilsonville, that's right down the highway from me. So familiar area.

Scott McMorrow:
Well, if you ever get a chance, you should ask for a tour of the plant. They love to give tours and it's a fabulous

Zach Peterson:
Facility. I just might have to do that. So obviously a very long and illustrious career, and I think it's really interesting that you got into doing this kind of consulting for Sam Tech right around the time that everybody else sites as the moment where they started to realize that you can't just lay out boards any which way you want to because that's where you start to notice all the signal integrity problems due to fast logic. Would you say that's fair? Yeah,

Scott McMorrow:
That's true. The oncoming, this was coming up in the late nineties, the signal integrity reflector was started back in the SI list was started back in the late nineties by Larry Smith and Ray Anderson from Sun Microsystems at the time. And that was where we all shared our craft learned from each other. Hi, A few secrets from people. But yes, what I used to say is, if you don't have a signal and integrity problem today, you're going to have one in the future. And I would say until recent times, most companies did not even consider signal integrity to be a discipline or a problem in their systems until they had systems fail. And so pretty much all of the companies that were the pioneers in signal integrity are ones that had systems boards, chips fail, and it became out of necessity. And of course, we drag the rest of the industry with us, and as we go faster and faster, everybody wants to go to the next standards BCI, gen 3, 4, 5, 6 a billion. And what was easy at the lower speeds becomes harder and harder and harder at the higher speeds. And so it necessitates having some knowledge of signal integrity these

Zach Peterson:
Days. Yeah, I agree. It's definitely mandatory for pretty much any designer. So this I think gets into what you're going to be doing at DesignCon because you're going to be giving a tutorial at DesignCon. So if you could just tell us about the tutorial that you'll be giving.

Scott McMorrow:
So the tutorial is about the steps in the processes for advanced printed circuit board connector or package or BGA launch design. And the idea is that I'm going to start out by teaching the basics, the physical basics of the launch, and I'm going to dispel a few myths along the way, and I'm going to break it down into what I call zones of control, those things that we have very good control over and those things that are similar throughout the via barrel and for differential or R fvs and how we can manipulate them and simplify the, there's a lot that it has to be controlled, especially as we get to 112 and then 2 24 gigabits per second. This is not easy. So what I try to do is take a problem that I would characterize as a whack-a-mole problem before you would just beat it into submission until you finally killed all the moles.

But still a problem will pop up and I take it into the realm of something that's more controllable, that's more understandable, that can inform you for all of your designs. And then I link this in with a tool that's fairly common in the industry in higher end signal integrity design. That's the Ansys HFSS 3D layout platform. And so we then step into here is how you're going to do the optimizations and the things that we can do to simplify that process. But also I built essentially a Python visualization package for 3D layout that automatically builds and generates the particular launch, gives it to you to the point where you have a whole list of different parameters you can control, all named with uniform naming conventions that are meaningful, all documented. And now you can start playing with, well, what if I do this? How do I get my routing out?

How do I stagger some of these launches in connectors and packages in order to facilitate routing, to facilitate lower crosstalk, to facilitate higher performance? And so putting it all in one place, it's not a simple job, but I've simplified it to the point where a human being can actually play with things literally in minutes. In minutes, we can build the launch, then start playing with the visual, how does it fit with all of the different pins in the connector or in the package? And then at that point you can start doing some simulations and if necessary co-design with us or with others where we help you in the process or you help yourselves or your colleagues. It makes it easy, for example, to the hardest thing to do in doing a printed circuit board launch design for a connector or a package is building it.

So planar tools like Allegro and Altium and others really don't interface to the signal integrity world. Well, they just send the whole layout over there. Well, that's too much to simulate and it's hard to break that down into simple elements. On the other side, you have the people that use Ansys H of SS 3D tools because it is a three-dimensional problem or a CST microwave studio or there are a few other tool in the industry, but it means you have to build up every piece individually while Ansys 3D layout is the intermediary. It is a planer design tool that has a concept of pads and pad stacks and vias. And so I can have a via with different antipas on each layers, and it's all containerized much like an EDA CAD system, but it simulates blazingly fast in the HFSS environment. So by writing a software package around that to basically automatically generate these things, I can generate them in and actually the tool will be available for people. You'll be able to generate them in the software in minutes. Something that sometimes would take weeks to do because you had to craft it by yourself. And if you make a mistake unraveling that mistake is very, very hard in these 3D design packages that are with 3D electrical solvers.

Zach Peterson:
Yeah, you called it a whack-A-mole problem, man, I totally relate to that one because I've done many via designs, whether for RF or high-speed, digital on differential pairs or whatever, but I always feel like you get it to where it's almost perfect and then you have to start playing with the parameters. And it's like, yeah, you improve it in the area where you want, but then you create a new problem in some other frequency range, and it's really difficult to get it just right because it involves so much manual tuning. And then each time you have to send it off to the simulation package. And like you said, it's either has to then be rebuilt manually or maybe you export it as a parasolid and then they can kind of recreate it from that. But it takes so much time, it's really difficult and especially testing every single little variation.

Scott McMorrow:
Oh, exactly. So the first thing I do is I try to simplify the variations to make it more a physics-based approach. We treat vias as periodically loaded transmission lines, which is, some people have talked about it in the past, but not in a uniform kind of way. I basically look at the different layering and each one creates different parasitic loading, but eventually we reach an asymptotic impedance. Well, once we reach that, we know we're at about the right place. The hardest thing is finding the right operating point for the via diameter and the anti pad sizes and the rest once you get it in the right range. Now it's fairly easy to look at what some of the parameters will do in some of the spacing. As an example, a lot of people start out with, okay, I'm going to design, I'm going to design a via transition for this thing and I'm going to use nine mil drills, 0.2, two five millimeter drills.

Great. Well, that might not be the optimum drill size for your design. So I fairly simply say, okay, let's make the via diameter programmable. Let's use standard values. Generally I use 0.2, 0.225 and 0.25 corresponding to eight, nine, and 10 mill drills ish. And let's look at the impedance through the via structure with about the smallest anti pad you can use and about the largest that you can use. And with that, I can now look at the terminal impedance or the asymptotic impedance of the system and go, okay, here's the one that gives me about the right range where I can control things. And it depends on the dielectric you're using. If you're using FR four and Anissa bar of about four, you can use smaller drills because the dielectric constants higher. And so that compensates for the inductance of the Via path. But if we're using low DK materials, say an ER of three, we sometimes have to step up to a larger via than we would like to have had.

And then I also throw a little bit of design for manufacturing. There's some manufacturing parameters in there for annular ring size si. People are really good at designing things that can't be manufactured and they get schooled by their layout team all the time. And so if you negotiate what the annular ring for the pad is and the annular ring for the minimum anti pad size with your layout team and with your fabricator, well, we can put that in the tool. And now you can perform the optimization based on those rules rather than something that you came up with in your mind. As an example, you start doing a design and you've designed a design with a 0.2 millimeter drill, and the SI person says, oh, well, it's not going to work for me. I need to step it up to a 0.2, two five or a point 0.25, but duh, we forget to change the annulus on the pad so the pad's too small. And when we send it over to layout, layout says, well, this can't work. I can't build this. So I try to take those. So I look at the layout problem, the manufacturing problems and the electromagnetics problems and a more holistic fashion

Zach Peterson:
In terms of the optimization procedure because there are so many parameters. And then you're implementing these different constraints. Is this a random search? Is this a guided search type of optimization

Scott McMorrow:
Procedure? It's an expert guided search and the signal integrity engineer do this. But I'll give you guidelines very simply. You start with, well, what's the pitch of the connector or the vias that you're going to be designing? We'll talk about differential vias. What's the signal to signal via pitch, and what's the signal to ground pitch? We start there, we build a structure and we basically build a through structure from the top of the board to the bottom of the board, and we actually include the balls that would interface to the component or the connector or the connector pins on either side. And we do a simulation of that. And all I'm looking for is what's the impedance of the structure? Because vias by themselves, if we didn't have planes, are a perfectly good transmission line. It's a perfectly good four wire transmission line. It has good performance, but it's extraordinarily high impedance.

We're talking a hundred twenty, a hundred thirty, a hundred forty os usually. And then we have planes in between, and those planes have parasitic capacitance. And so the planes periodically load this uniform transmission line with capacitance. Well, once we pass a waveform down there with a particular rise time, once we've reached the electrical length or the physical length that is equivalent to the rise time of the edge, we now reach a plateau. That's our impedance. So the first thing we do is literally I do six, yeah, six simulations, three different via sizes 0.2, 0.225 and 0.25 and then two different anti pad sizes minimum, which is usually 600. Basically a 0.6 millimeter ring opening around the pad up to maybe 900.9 millimeters. So we give it a range. And so for every via, I see what the impedance is of the small anti pad and the large anti pad. And then I have these, I've got six different simulations that I've run in my environment on one processor with 32 cores.

These run in about five to 10 minutes. So as soon as I see that I have basically this step, this basically this pulse looks like a pulse function of different terminal impedances from the target, and I look for the ones that are really close to it, that's it. Then I can now take those and optimize that particular anti pad size to get it closer to the target impedance that I want. We also identify that there's usually two types of layer passings in a printed circuit board. The first is thin plane layers, which are grounds surrounding traces. They're usually 0.6 mil thick. Then there are thick planes used for power, power in the powers in the grounds for the power system. They're usually thicker, they're often three mills thick. Well, as you can imagine, the parasitic capacitance is significantly higher for the power plane passings than it is for the signal ground reference passings.

And so the anti pad size is different. So we modify that. And again, just simple steps. This is a linear problem. So we literally, if we just have two points for anti pad sizes and we see a high impedance here and a low impedance here, we can look at it and go, I think it's going to be about right here. That's a good anti pad size. Then we can go in and run some targeted simulations, just dithering that by 0.1 millimeter 0.05 millimeters to get us a better balance. And so what we try to do is balance the trace return path planes with the power planes to flatten the via impedance. Once we've got that, we've got the drill size and the via impedance via is all taken care of. We're done with respect to the via stack itself. Now what we're left with is the back drill section and the trace escape section.

And what we're going to do is we're going to control the anti pad size on the plane above the trace and the plane below the trace, and we're going to change how the differential pair comes in and wise over into the vias. We can move that point and that'll help in tuning, we can change the bottom anti pad and we can actually slide it and offset it to create better a quicker connection to the plane plane underneath. And then we can simulate our back drilling and it's really that simple. And we start out with something that for oh, 56 gigabits per second, literally about an hour and you're good enough and you're done when you go to one 12, well, we just doubled the nyquist frequency. It takes maybe an hour and a half to get everything done good enough. And then finally, if we're going to 2 24, you're going to spend some time, but we can still do this.

We can literally, if you have enough compute cycles and cores, we can have a near optimal design done in days. And so we can get these things done fast quickly. You learn from them. And then the next step is, alright, now that I've got my via stack design, I'm getting the return loss that I want, the impedance control that I want, now let's look at the crosstalk. And so we build an array of these. It turns out an array of launches still has the same, each launch has still has the same impedance as the original one. We don't have to readjust that. All we have to do now is go, okay, where's our routing going to go? And based on that, do we need to put any extra ground vs in to shield crosstalk? And so what we basically do is work with our layout person to get the routing directions that they want, the directionality they want.

Then there's always some space and we figure out how to cleverly put vias there in those spaces. That's the process. Along with this process, we can actually change the array in any linear connector or linear package. In some cases we can actually change the offsetting the routing direction and we can do some things to beneficially and preferentially allow us to say if we want to route vertically, we basically offset launches to provide vertical channels or maybe we keep them all flat and we route out one direction and another to create horizontal channels. So I try to encompass all that in the training. So it's sort of a masterclass in how to go through the whole process in a, not so much a heuristic, but a holistic fashion and a logical progression for the things that you have to do in the design.

Zach Peterson:
Yeah, that is quite a bit, but of course super interesting. One thing that I think someone would ask, and of course I'm curious, are these just coaxial, whether they're differential or single-ended coaxial, does it apply to blind and buried? Can you do blind buried and staggered? Can you do mix and match?

Scott McMorrow:
Well, so the answer is I'm dealing with, I've dealt with the via problem to start with, and most connectors are what I'll call linear connectors. That is all of the balls are in a line. So we start with linear connectors and often they have either, if they're differential connectors, two signals, one or two grounds between the pairs. And so we can build the breakouts and we can build the launches based on that. So the idea is to take standard connectors, which are often linear and do that, but we can have offset connectors or offset things. There's some connectors where the pins are offset back and forth. There's a separate breakout generator that for rf, single-ended launches and that will be a coaxial design, but most of them will be just simply ground signal, signal ground via designs optimal for routing high density boards. As you become what we found for differential signals coaxial surrounding a via with a lot of grounds signal vias with grounds, it looks pretty, it's near impossible to route in real boards.

It's costly and it often causes other problems like basically enclosed cavities that can actually resonate. And so you start having these resonance points and suck outs that you didn't want to have. So we try to stay away from that as much as possible. We allow some of the energy to dissipate in the board, but we want to guide it to the areas where there aren't any signals. And so that's what ground stitch vs are. But we try to do that in a routing aware fashion so that we don't cause more problems than we'd like to. I like to keep my layout people liking me instead of hating me and trust me, they hate a lot of signal integrity engineers.

Zach Peterson:
You bring up the staggered differential and that there's two big areas where I think that really is important is VPX connectors and then also on the bottom side of some packaging, especially targeting the 112 G two 20 4G types of channels.

Scott McMorrow:
Yeah, exactly. So we work with all of that. The tool actually allows me to change the stagger not only in the balls and we'll basically pre-configure the ball locations for our particular connectors, but in the same thing for packages one millimeter and 0.8 millimeter packaging. But we also separate the ball locations from the via locations. So basically I can incorporate via in pad or offset vias. And the offset vias can be basically adjacent to or basically co-located or slightly offset. So they basically create almost like a figure eight pattern or we can actually have breakout traces with room for solder mask and everything. So I incorporate all that and I can break them out in the north direction or the south direction. I can move the vias north or south from a straight line and the trace routing can go south or north and in some cases the trace routing and the VS can be placed diagon diagonally like we often do in packaging breakouts, right?

We generally put the V in the dead center, kind of like a number five dice pattern between the balls. I envisioned all of those things and incorporate all those things and it makes it easy to visualize. It also makes it really easy to compare the differences. There's a cost difference between doing via and pad or an offset via five to 10% or so to do the via fill, cap and plate. And you can get really high performance products out of that. But if you can do the same thing with an offset dogbone via breakout, well maybe that's the way to go. And you can very simply just with one parameter change that breakout from a via in pad to an offset via breakout and do two simulations and you've got the AB comparison and you can say, does it meet my requirements or not? There's actually some cases where the offset pattern where we actually do a dog breakout works better because it provides a little bit of extra inductance to compensate for vias that are very pads and balls and things that are very close together.

And then for RFV, we use a coaxial through drill pattern. I started with through drills quite simply because they're the cheapest. If you can do a design totally with through drills, why wouldn't you? Would you go to And generally I've done lots of microvia designs. I've designed packages, I've designed 8 2 8 buildup packages and both staggered or we used to call spiral microvias or stacked microvias. Well stacked vias are expensive and those wonderful little, and of course we can design a board with microvias on the top cap layer on the bottom cap layer and lots of people do it. The problem with micro V is if you have to go more than one layer, it starts becoming really expensive or you transition to drilled vias and as soon as you do that, well you have your, yeah, micro V is small, but you can't place it on top of a drilled via, so you actually physically take up more space on the inner layers of your board at the layer that you transition from the microvia to the through via. So I prefer not to do that. I like to push technology. I like to hope that the technology keeps going to where we can have smaller and smaller drills with higher aspect ratios and use them to do our designs because microvia is quite frankly, you're a 20 to 40% cost add depending on what you're doing and in some cases even more than that. So I try to stay with the cheap approaches so that people can actually build these in high volume.

Zach Peterson:
Yeah, I think you're thinking on this makes total sense. One thing I wanted to ask you was about the workflow. The way I use the kind of simulation for these types of transitions is on the front end you prepare what you envision the transition to look like for your stack up and give that to the layout person. They're going to implement that where it needs to be implemented and then they kind of work around that. So you really use it as a constraint. Is that your thinking here as well?

Scott McMorrow:
It is, but I'm modifying that constraint a bit. So the first off is constraint. Number one is what's the connector that you're using? And so basically we basically prepackaged that so that you basically load in the connector type you want, and a functional breakout is actually generated starting, it's the starting point. The VS may not be sized correctly, the antipas not, may not be quite correct, but then in the process you have the ability to choose two things. We always get in the breakout generator. That's A through via, which is a launch on the top basically BGA on the top and a B, GA on the bottom launching through the board. That's what we use to adjust the antipas and the spacings and everything. And then the trace escape, and you can choose what layer you want it to escape on. The tool allows you to create a generic stackup from four layers up to 42 layers with a programmable dielectric.

In this case it's a uniform dielectric, but it's a complete de GeoVic SAR car model used in Ansys 3D layout. And it's fully programmable. It includes anisotropic behaviors. So we can actually look at the XY plain dielectric difference between the XY and the Z directions, which is important for tuning vias. And since this is a via tool, there has to be the ability to enter that. And so we enter that as essentially a percentage correction factor that you have to either know derive guess or, but anything's better than having flat dielectric constant in all directions because we know that's wrong. So we do that, but then we also have the ability to look, if we're looking for crosstalk, we can do an array of one row with two columns, so the in row crosstalk and then one row two rows with one column for row to row crosstalk.

So we can now see what do we have to do there. But I can also build an array of two by two, three by three, four by four, five by five, six by six, seven by seven, eight by eight. Boom, they're all built. Now you can play with the offsets and staggering using it's all totally parameterized. You don't have to do anything. You don't have to move anything. The parameters move it for you. And what I envision is people that have access to this tool could actually sit there with their layout designer and try different patterns I and look at them and visually say, because they'll sit there and go, no, you can't possibly route through that. You don't have enough space. What if I do this? What if I do that? We'll have prebuilt patterns that are optimized for best vertical escape with the largest available channels that you can have.

Our largest channel spacing, so differential pair spacing going through and the best horizontal channels. And so you can optimize or compromise any way you want. And once you get to that, you've got that essentially a visual conversation with your layout team. You can sit there with the tool and make some measurements and go, okay, here's, I've got 1.2 millimeters between these vias. Is that going to be enough to put our big fat traces through there, yes or no? Okay, we're done. So it makes that process. I'm trying to force the routing visualization process back to the signal integrity person's hands. You then finish the design, finish it, and in 3D layout we can output D xfs. So layer by layer, DXF, or you can shoot pictures of the, now I no longer if I have a 36 layer board, it would be stupid for me to document every 36 layers.

But what we're going to document are the different zones that we have programmable. So the zone at the top of the board near the balls, the zone and the thin trace layers, that's another. And that all of those thin trace layer planes, we'll get the same antipas and then we'll have the same one for the thick plane layers. And then we'll have the trace breakout and we'll just say, okay, the layer above the trace breakout gets this, the layer below the trace breakout gets that, and now the layout department can build those. We in our design flow at SAM Tech, we build launches as physical components that overlay on top of the pads. So we build, so the ground, the antipas are all encapsulated into a hierarchical object that then gets placed in the schematic as a separate object. So your layer six breakout is a pattern, is a physical design object in the schematic tool because we're actually thinking forward about which layers are we going to route these things on.

And if the layout person wants to change from layer six to layer eight, well they just have to bring in the other object and back anitate the schematic. The beauty of this is that in many layout tools, if you have hierarchy, if you encapsulate the layout of the launches as a physical component, you only have to change each physical component once to make a change. I want to make a change for performance. Or the layout team says, we need to change from this drill to that drill. You need to reoptimize great when it's done, they update the physical component, press update, boom. Everything in the design is updated. And trust me, when you're dealing with boards that have hundreds if not thousands of launches in them, this is not only a time S saver, it is a lifesaver because before we started using this, I developed this methodology with one of my layout engineers years ago when I was consulting because I got tired of asking the question when I got the board back, why are all these launches identical except for this one? Well, and the answer was the update process didn't work out. The cut and paste didn't work correctly or I just didn't, the cut and paste or the layout person didn't do the cut and paste. This makes this a seamless and simplified process, and if you implement it, it becomes error free.

Zach Peterson:
With you supervising so many people in the signal integrity group at Sam Tech, I'm sure that there are plenty of people who are varying in the quality of the launches that they design as well as probably a lot of duplicate work. How do you guys handle that? Does this tool help you handle that?

Scott McMorrow:
Well, we're just rolling out the tool, so I'll start with I don't supervise anybody. Okay.

Zach Peterson:
My mistake

Scott McMorrow:
As a strategic technologist, what I'm looking for are problems that need to be solved. And so I look for things that nobody else is looking at. And one of the things was we literally build probably a thousand launches a year that would not be, I know just one of the guys that I work with does at least a hundred a year because we do this as a service for our customers. And I started looking at them and pulling my hair out and I have a lot of hair going, why do we keep doing almost exactly the same launch, but it's different. Why do we keep wasting all of this time? And then I also started thinking about how do we do what ifs? What if I change from a dielectric a three to a 3.5 because it's a lot cheaper? I'm obviously I got to change the launch.

How do I make that easy? Well, in the tool, I'd literally just change the dielectric constant and reoptimize and goes through the same process again, and I kind of know where I am, and so I know what it might take. You start getting a feel for how to do things. The idea behind this was simply to save us time internally and then the realization that we also want to save our customers time. And I don't want engineers at Sam Tech to be designing every launch for the customers that we have. And we have some customers that will design eight different layers of transition of launches, maybe multiple types of connectors. So there might be 10, 15, 20. And then in the process, their layout department is saying, oh, well you can't do this because these are our design rules. And so there's all of this thrash that goes around.

And so if a customer of ours has the tool and we have the tool and they have the same simulation environment that we do, then we can send them prototypes, they can look at it, review it, review it with their layout engineers, we can teach them how to use it, and then eventually reduce that loop, that design iterate loop that we all go through over and over again. So that was the other thing that I do is I have uniform naming conventions and so we'll all be talking the same language now via drill side. The name for the name for a via drill size is literally via signal, via drill size, via drill size signal, drill size signal via or something like that. I've forgotten the exact names. And they're all documented with documentation that tells you what they do. And so now we're talking about the same things, God, how many signal integrity engineers don't understand about pad annular rings and why they're there.

They don't understand that they can't put a trace that the anti pad annular ring is really the stop point where any trace metal can come to. They don't know that because they're routing it on over top of a power plane or a ground plane and the metal's filled in. They don't see that imaginary ring that guards against delamination when the drill is at its extreme in the manufacturing process. So many signal integrity engineers don't understand that the pad is simply the circular probability of error of the drill via position in the manufacturing process due to drill placement and wander in the process. So this tool helps to at least unify some of those things so that we can talk about them and understand why they're necessary.

Zach Peterson:
Well, this is all extremely interesting and I would love to play around with it if I can get access to it. If anyone is interested in learning more, where can they find you at the DesignCon? So what day in what room, and then how would they be able to get access to this after DesignCon?

Scott McMorrow:
So I don't recall the room, but the tutorial is literally the first tutorial on Tuesday, the first tutorial session. It's a two and a half hour session on Tuesday at DesignCon. I think it's 9:00 AM and I am going to kill myself. I'm going to have lots of coffee because I'm not a morning person, although I'll be jet lagged coming from the east coast, so it'll actually be later for me, so it won't be so bad. Then I will be around the SAM Tech booth if I'm not, give your card and information to anybody at the SAM Tech booth at the front counter and they will find me, I can set up a tutorial, a short demonstration with you. The idea is this tool will be available for anybody that uses the Ansys HFSS environment.

If you use Sam Tech connectors, then you'll be able to use this on selected SAM Tech connectors and we'll be issuing more and more throughout the year. And then otherwise you'll also be able to use it on one millimeter and maybe if I build it up in time 0.8 millimeter pitch BGAs because everybody has to do a, B, G, A breakout and I'll do a couple of different variants of that. We don't get a lot of latitude in those unfortunately because there's so many darn balls and V is being punched through, but we have a few tricks we can play.

Zach Peterson:
Well, this is great. Thank you so much for being with us today and I hope everybody checks out the show notes. They can learn more about what you're doing and the information for finding you at DesignCon will be in the show notes. So anyone that's interested, make sure to check that

Scott McMorrow:
Out. Alright, Zach, thank you for having me. It's been a

Zach Peterson:
Pleasure. Thank you so much again to everyone that's out there watching. We have been talking with Scott McMorrow, strategic technologist for Signal Integrity products at Sam Tech. As I said earlier, make sure to check out the show notes and you can get more information about Scot's tutorial at DesignCon. Also, if you're watching on YouTube, make sure to hit that subscribe button, hit that like button. You'll be able to keep up with all of our podcast episodes and tutorials as they come out. And last but not least, don't stop learning, stay on track and we'll see you next time. Thanks everybody.