What to Spec Around Wide-Bandgap Switches

This article is a practical spec guide for engineers designing silicon carbide (SiC) and gallium nitride (GaN)based power stages. It focuses on the decisions that control first-spin behavior, including edge control, isolation performance, measurement integrity, magnetics readiness, and the layout constraints that make those specs real on a PCB.

If you want the context behind why these items matter, read The Board-Level Trends Shaping Wide-Bandgap Power. Then use this guide to develop requirements you can hand to schematic and layout. At the end of the article, you will find a first-spin checklist you can drop into a project requirements sheet.

Key Takeaways

• Wide-bandgap designs succeed or fail on the supporting ecosystem. Gate drive, isolation, sensing, magnetics, and layout constraints set switching behavior, EMI, and robustness.
• The fastest path to a clean first spin starts with requirements. Lock down operating envelope and transient targets, choose your isolation strategy, then drivers and sensing. After that, pick magnetics, then enforce layout and validation gates. 
• Specs that felt secondary with silicon MOSFETs become gating specs with SiC and GaN. Common-mode behavior, loop inductance, measurement integrity, and fault timing become first-order design constraints.

Start With System Constraints, Then Lock a Requirements Sheet

Wide-bandgap leaves little room for ambiguity. If key constraints stay informal, the first layout becomes a lab experiment. The fix is documentation. Start by defining four design inputs:

• Operating envelope: bus range, surge assumption, temperature range, and environment notes that affect insulation (altitude, condensation, conductive dust).
• Switching targets: frequency range plus an edge-rate intent tied to a goal, such as thermal headroom or EMI margin.
• Transient targets: allowed switch-node overshoot and ringing envelope, plus allowed gate overshoot and undershoot.
• Fault philosophy: what must trip immediately, what must ride through, and what data you need for debug.

This documentation will drive package choice, placement, barrier location, and the amount of tuning space you reserve. 

Device-Level Specs That Change With SiC and GaN

Voltage and current ratings are the entry ticket, but dynamic behavior and parasitics determine how hard it will be to stabilize the board. Start with voltage class and a margin policy that accounts for overshoot. Then review the dynamic levers that shape ringing and loss:

• Gate charge versus your driver current capability
• Output capacitance (Coss) and stored energy (Eoss) across the operating voltage range
• Reverse conduction behavior and deadtime expectations

Finally, treat the package as part of the circuit. Kelvin source pins, low-inductance packages, and modules exist to control parasitics. If you choose a higher-parasitic package, plan for slower edges, more damping, or more EMI work.

Gate Driver Specs That Control Outcomes

Gate drive defines edge control, false turn-on immunity, and fault behavior. 

Drive Strength and Edge Control

Peak source and sink current sets how quickly you can move charge on and off the gate. Specify it for your intended edge-rate range and switching frequency. Plan for independent turn-on and turn-off control via split gate resistors or separate outputs.

Decide whether edge-rate control is resistor-led or driver-feature-led, and standardize on one default across projects. Leave room on the PCB for tuning with alternate gate resistors, ferrites, and optional small RC networks. Add footprints for gate-source clamps if the gate voltage window is tight or if you expect cable-induced transients.

Timing and Deadtime Policy

Propagation delay and delay matching matter more as edges get faster. Specify a deadtime policy early and tie it to reverse conduction expectations and protection timing. For tight designs, include delay variation over temperature and supply.

False Turn-On Control

High rate of change of voltage (dV/dt) can induce gate voltage through Miller coupling. The simplest solution is usually a Miller clamp, though negative gate bias can help if you're willing to accept constraints around undervoltage lock-out (UVLO) behavior and safe shutdown.

Protection and Fault Behavior

Define your protection features and their behavior, including desaturation detection (DESAT), soft turn-off, UVLO thresholds, fault reporting, latching, and restart policy. For fault and DESAT routing, set noise immunity expectations and keep these traces away from the switch node. 

Layout Dependencies As Requirements

Your driver choice comes with layout assumptions that should be documented. Write down placement and routing rules early:

• Driver close to the switch, with a maximum gate loop length or a “same-side” rule
• Gate and return routed as a tight pair with a clear return path
• Kelvin source return required when available, and a defined alternative when it is not
• Mandatory pads for tuning parts in compliance-sensitive designs
• Gate loop inductance target or maximum loop perimeter target

Isolation and Insulation Coordination

Isolation must satisfy safety requirements and survive common-mode transients without corrupting control and sensing signals.

Start by deciding whether each barrier requires basic or reinforced insulation. Define working voltage and surge assumptions, then translate them into creepage and clearance targets. Those targets drive package choice, board keepouts, and sometimes mechanical geometry.

Then set a common-mode transient immunity (CMTI) target that’s aligned with the expected dV/dt at the barrier. Consider barrier capacitance, as it can couple noise into the control and measurement references. Treat barrier placement as an electric-field management problem, and keep the barrier and its returns out of the switch-node near field.

Finally, choose a delay and robustness profile that fits your control loop and protection timing, then lock in placement.

Current Sensing and the Measurement Chain

Wide-bandgap raises the stakes on measurement fidelity. The signal has to stay trustworthy in a louder environment. Define the purpose first: protection response, control loop stability, efficiency optimization, or metering. Then choose the sensing approach that fits:

• Shunt plus isolated amplifier or modulator: Strong bandwidth and accuracy, demanding Kelvin routing.
• Hall sensors: Galvanic isolation and low insertion loss, but watch bandwidth, offset, and drift.
• Current transformer or Rogowski: Strong for fast transients and AC content, but with higher integration and calibration effort.

Once you've chosen the approach, specify the chain. Set a bandwidth target and noise budget. Decide where filtering happens and what it must preserve. Specify Kelvin pads and a routing rule that keeps the sense pair away from the switch node and its return currents. 

If the sensing output crosses an isolation barrier, specify both the barrier class and the required common-mode behavior.

Magnetics and Passives

Higher switching frequency and faster edges can shrink magnetics, but they increase sensitivity to AC loss and parasitics, including leakage inductance and winding capacitance.

Magnetics

Specify core material, saturation current at defined thermal conditions, allowable temperature rise, winding construction, and leakage inductance targets tied to ringing or soft-switching margin. If you plan to push frequency, call out AC loss management as a requirement. Proximity and skin effects can dominate quickly, especially in compact windings and planar structures.

Passives

Define your DC-link architecture, including the roles of bulk capacitance and local ceramics, plus placement rules. At fast edges, ESL and geometry matter as much as capacitance value. Specify damping intent early. Decide whether snubbers are allowed, where they go, and what power dissipation you can tolerate.

Layout Rules and Validation Gates

Critical Loop Control

Control the commutation loop: plan the PCB layout by placing local DC-link ceramics tight to the half-bridge and minimizing the loop area through device pins and vias. Control the gate loop by placing the driver close, routing the gate and return as a tight pair, and using Kelvin returns when possible. Manage the switch node by keeping the copper area compact, isolating it from quiet signals, and applying explicit keepouts. For more details, see Wolfspeed’s PCB Layout Techniques For Discrete SiC MOSFETs.

Validation Planning

Before the first build, plan your validation approach. Define probe points that support differential probing without adding inductance, and set up an EMI pre-scan covering conducted checks and near-field scans around the switch node. Decide what must be proven before iteration, such as overshoot envelope, thermal rise, and a baseline EMI signature you can tune. For more on this, see Renesas’ Application Note, Printed Circuit Board Layout and Probing for GaN Power Switches.

A Practical Workflow That Reduces Respins

Wide-bandgap designs reward teams that spec the ecosystem, then validate it like a system. If you lock down the driver, isolation, sensing, protection, and layout constraints up front, the first spin becomes a structured verification build instead of a gamble.

Use the checklist to turn “fast switching” into explicit numbers, then map those numbers to footprints, alternates, and probe points before layout hardens. The result is cleaner waveforms, fewer late-stage surprises, and a power stage you can qualify, manufacture, and source with confidence.

First-Spin Spec Checklist

A. System Targets 

[ ] Bus voltage range and max surge assumption

[ ] Allowed switch-node overshoot policy (explicit margin)

[ ] Target switching frequency range and edge-rate intent

[ ] Efficiency target and EMI target for first spin

B. Gate Drive 

[ ] Peak source and sink current requirement (numeric)

[ ] Propagation delay and matching requirement, plus deadtime strategy

[ ] Miller clamp: required or optional

[ ] Negative bias policy: none, limited, or mandatory 

[ ] Protection features: DESAT, soft turn-off, UVLO thresholds, fault reporting 

[ ] Gate resistor strategy: split on/off, plus pads for tuning options 

C. Isolation and Barrier

[ ] Insulation class: basic or reinforced 

[ ] Working voltage class and creepage and clearance targets

[ ] CMTI target aligned with expected dV/dt

[ ] Barrier placement rule: keep barrier parts away from switch-node fields 

[ ] Barrier crossing routing rule: no parallel runs with switch node, clean returns 

D. Current Sensing Chain

[ ] Sensing method choice and bandwidth target

[ ] Noise budget and filtering plan, including where the filter lives

[ ] Kelvin routing requirement for shunt measurements

[ ] Isolation requirement for sensing chain and reference strategy

[ ] Protection trigger path: clean, short, and separated from switch node coupling 

E. Layout And Validation Gates

[ ] Commutation loop placement rule: DC-link ceramics at the half-bridge 

[ ] Gate loop placement rule: driver near gate, Kelvin return preferred 

[ ] Switch-node copper rule: minimum area, explicit keepouts 

[ ] Probe plan: where to measure Vgs, Vds, current, and common-mode noise 

[ ] EMI pre-scan plan: conducted and near-field checks tied to the first build